From: Leon Alrae <leon.alrae@imgtec.com>
To: "Maciej W. Rozycki" <macro@codesourcery.com>, qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses
Date: Tue, 2 Dec 2014 10:52:27 +0000 [thread overview]
Message-ID: <547D99EB.5040500@imgtec.com> (raw)
In-Reply-To: <alpine.DEB.1.10.1411180320380.2881@tp.orcam.me.uk>
On 18/11/2014 03:59, Maciej W. Rozycki wrote:
> Please note that for this validation I'm using an artificial microMIPS
> processor that also has an FPU implemented, so that our microMIPS FP
> support is correctly validated too (I don't really know if there exists
> any real microMIPS processor that includes an FPU; if so, then it would
> be good to add it to the list our supported configurations).
FYI, there are real CPUs which support microMIPS and include FPU, for
example microAptivUC.
> qemu-mips-config3-isaonexc.diff
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
next prev parent reply other threads:[~2014-12-02 10:52 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-18 3:59 [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses Maciej W. Rozycki
2014-12-02 10:52 ` Leon Alrae [this message]
2014-12-02 11:44 ` Maciej W. Rozycki
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