Re: [PATCH v2 3/3] arm64: dts: rockchip: Add Luckfox Omni3576 Board support

[John Clark <inindev@gmail.com>]

On 5/4/25 7:01 PM, Andrew Lunn wrote:
> On Sun, May 04, 2025 at 05:02:33PM -0400, John Clark wrote:
>> On 5/4/25 10:12 AM, Andrew Lunn wrote:
>>>>> +&gmac0 {
>>>>> +	clock_in_out = "output";
>>>>> +	phy-handle = <&rgmii_phy0>;
>>>>> +	phy-mode = "rgmii-rxid";
>>>>
>>>> See Andrew's remark on v1 of this patch.
>>>
>>> Hi John
>>>
>>> If you have questions, please ask. It is not a good idea to silently
>>> ignore reviewers comments. Either do something about it, ask
>>> questions, or politely argue why the reviewer is wrong, because
>>> sometimes we are.
>>>
>> Hi Andrew,
>> Thanks for your feedback and the link to the RGMII delays discussion. I
>> assumed you suggested switching to phy-mode = "rgmii-id" from rgmii-rxid.
>> The vendor’s downstream kernel uses rgmii-rxid with tx_delay = <0x20>, as
>> shown in my post. I tried rgmii-id and removed tx_delay, but the interface
>> failed to get a DHCP address. Reverting to rgmii-rxid with the delay
>> restored functionality. Any advice on correctly configuring rgmii-id or
>> adjusting delays for this board?
> 
> What PHY is it? Are you using the correct PHY driver for it, or
> genphy?
 >

This fails:

&gmac0 {
         clock_in_out = "output";
         phy-handle = <&rgmii_phy0>;
         phy-mode = "rgmii-id";
         pinctrl-names = "default";
         pinctrl-0 = <&eth0m0_miim
                      &eth0m0_tx_bus2
                      &eth0m0_rx_bus2
                      &eth0m0_rgmii_clk
                      &eth0m0_rgmii_bus
                      &ethm0_clk0_25m_out>;
         status = "okay";
};

&mdio0 {
         rgmii_phy0: ethernet-phy@0 {
                 compatible = "ethernet-phy-ieee802.3-c22";
                 reg = <0x0>;
                 clocks = <&cru REFCLKO25M_GMAC0_OUT>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&gmac0_rst>;
                 reset-assert-us = <20000>;
                 reset-deassert-us = <100000>;
                 reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
         };
};

&pinctrl {
         gmac {
                 gmac0_rst: gmac0-rst {
                         rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO 
&pcfg_pull_none>;
                 };
         };
};


This works:

&gmac0 {
         clock_in_out = "output";
         phy-handle = <&rgmii_phy0>;
         phy-mode = "rgmii-rxid";
         pinctrl-names = "default";
         pinctrl-0 = <&eth0m0_miim
                      &eth0m0_tx_bus2
                      &eth0m0_rx_bus2
                      &eth0m0_rgmii_clk
                      &eth0m0_rgmii_bus
                      &ethm0_clk0_25m_out>;
         tx_delay = <0x20>;
         status = "okay";
};

&mdio0 {
         rgmii_phy0: ethernet-phy@0 {
                 compatible = "ethernet-phy-ieee802.3-c22";
                 reg = <0x0>;
                 clocks = <&cru REFCLKO25M_GMAC0_OUT>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&gmac0_rst>;
                 reset-assert-us = <20000>;
                 reset-deassert-us = <100000>;
                 reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
         };
};

&pinctrl {
         gmac {
                 gmac0_rst: gmac0-rst {
                         rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO 
&pcfg_pull_none>;
                 };
         };
};

> 
> rk3576-rock-4d.dts and rk3576-armsom-sige5.dts show that it is
> possible to use this SoC with the correct 'rgmii-id',
> 
> 	Andrew