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* [U-Boot] [PATCH 2/3] B4860QDS: SGMII related updates
@ 2014-11-12 10:30 Shaveta Leekha
  2014-12-05 16:32 ` York Sun
  0 siblings, 1 reply; 3+ messages in thread
From: Shaveta Leekha @ 2014-11-12 10:30 UTC (permalink / raw)
  To: u-boot

    - Enable SGMII support for 0x8d Serdes 2 protocol.
    - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
    - Updated debug statement
    - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
    - Rename onboard PHY address defines for more readability
    - Add these new Defines in B4860QDS.h file

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Change-Id: I4d9a8c602bdaac8404577ab9642f8c5f37ac7cdc
Reviewed-on: http://git.am.freescale.net:8181/23353
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yusong Sun <yorksun@freescale.com>
---
 board/freescale/b4860qds/eth_b4860qds.c |   64 ++++++++++++++++++------------
 include/configs/B4860QDS.h              |    4 +-
 2 files changed, 40 insertions(+), 28 deletions(-)

diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 12df9a8..2726cd2 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
 		 * Lanes: A,B,C,D: PCI
 		 * Lanes: E,F,G,H: XAUI2
 		 */
+	case 0xb1:
 	case 0xb2:
+	case 0x8c:
+	case 0x8d:
 		/*
 		 * Configuration:
 		 * SERDES: 2
@@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
 	 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
 	 * 6 to on board SGMII phys
 	 */
-	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
 
 	switch (serdes1_prtcl) {
 	case 0x29:
 	case 0x2a:
 		/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
-		debug("Setting phy addresses for FM1_DTSEC5: %x and"
-			"FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
-			CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
+		      CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+		      CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC5,
-				CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+				CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6,
-				CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+				CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
 		break;
 #ifdef CONFIG_PPC_B4420
 	case 0x17:
 	case 0x18:
 		/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
-		debug("Setting phy addresses for FM1_DTSEC3: %x and"
-			"FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
-			CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
+		      CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+		      CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
 		/* Fixing Serdes clock by programming FPGA register */
 		QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
 		fm_info_set_phy_address(FM1_DTSEC3,
-				CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+				CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC4,
-				CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+				CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
 		break;
 #endif
 	default:
@@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
 	switch (serdes2_prtcl) {
 	case 0x17:
 	case 0x18:
-		debug("Setting phy addresses on SGMII Riser card for"
-				"FM1_DTSEC ports: \n");
+		debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC1,
 				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2,
@@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
 		break;
 	case 0x48:
 	case 0x49:
-		debug("Setting phy addresses on SGMII Riser card for"
-				"FM1_DTSEC ports: \n");
+		debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC1,
 				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2,
@@ -255,10 +258,12 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC3,
 				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
 		break;
-	case 0x8d:
+	case 0xb1:
 	case 0xb2:
-		debug("Setting phy addresses on SGMII Riser card for"
-				"FM1_DTSEC ports: \n");
+	case 0x8c:
+	case 0x8d:
+		debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
+		      CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC3,
 				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC4,
@@ -266,18 +271,18 @@ int board_eth_init(bd_t *bis)
 		break;
 	case 0x98:
 		/* XAUI in Slot1 and Slot2 */
-		debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
+		debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
 		      CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM1_10GEC1,
 					CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
-		debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+		debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
 		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
 		fm_info_set_phy_address(FM1_10GEC2,
 					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
 		break;
 	case 0x9E:
 		/* XAUI in Slot2 */
-		debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+		debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
 		      CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
 		fm_info_set_phy_address(FM1_10GEC2,
 					CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
@@ -329,17 +334,20 @@ int board_eth_init(bd_t *bis)
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
 			fm_info_set_mdio(i,
-					 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+					 miiphy_get_dev_by_name
+					 (DEFAULT_FM_TGEC_MDIO_NAME));
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
 			break;
 		default:
-			printf("Fman1: 10GSEC%u set to unknown interface %i\n",
+			printf("Fman1: TGEC%u set to unknown interface %i\n",
 			       idx + 1, fm_info_get_enet_if(i));
 			fm_info_set_phy_address(i, 0);
 			break;
 		}
 	}
 
-
 	cpu_eth_init(bis);
 #endif
 
@@ -357,15 +365,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 
 		sprintf(alias, "phy_sgmii_%x", phy);
 		fdt_set_phy_handle(fdt, compat, addr, alias);
+		fdt_status_okay_by_alias(fdt, alias);
 	}
 }
 
+/*
+ * Set status to disabled for unused ethernet node
+ */
 void fdt_fixup_board_enet(void *fdt)
 {
 	int i;
 	char alias[32];
 
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+	for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_NONE:
 			sprintf(alias, "ethernet%u", i);
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index dc1a9bc..b47b9de 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void);
 #endif	/* CONFIG_PCI */
 
 #ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x10
-#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR	0x11
+#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
+#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 
 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
-- 
1.7.6.GIT

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* [U-Boot] [PATCH 1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420
@ 2014-11-12 10:10 Shaveta Leekha
  2014-11-12 10:10 ` [U-Boot] [PATCH 2/3] B4860QDS: SGMII related updates Shaveta Leekha
  0 siblings, 1 reply; 3+ messages in thread
From: Shaveta Leekha @ 2014-11-12 10:10 UTC (permalink / raw)
  To: u-boot

Addded Alternate options with LC VCO for following protocols:
0x02 --> 0x01
0x08 --> 0x07
0x18 --> 0x17
0x1E --> 0x1D
0x49 --> 0x48
0x6F --> 0x6E
0x9A --> 0x99
0x9E --> 0x9D

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>i
Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2
Reviewed-on: http://git.am.freescale.net:8181/23352
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yusong Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/b4860_serdes.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index cf18be5..63172de 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,6 +18,8 @@ struct serdes_config {
 #ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
+	{0x01, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x02, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x06, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x07, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x08, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, NONE, NONE} },
 	{0x0F, {NONE, NONE, CPRI6, CPRI5,
 		CPRI4, CPRI3, NONE, NONE} },
+	{0x17, {NONE, NONE,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
 	{0x18, {NONE, NONE,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
 	{0x1B, {NONE, NONE,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
+	{0x1D, {NONE, NONE, AURORA, AURORA,
+		NONE, NONE, NONE, NONE} },
 	{0x1E, {NONE, NONE, AURORA, AURORA,
 		NONE, NONE, NONE, NONE} },
 	{0x21, {NONE, NONE, AURORA, AURORA,
@@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
+	{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		NONE, NONE, NONE, NONE} },
 	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		NONE, NONE, NONE, NONE} },
 	{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		NONE, NONE, NONE, NONE} },
+	{0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, AURORA, NONE, NONE, NONE, NONE} },
 	{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
 	{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
+	{0x99, {PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
 	{0x9A, {PCIE1, PCIE1,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
+	{0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
+		NONE, NONE, NONE, NONE} },
 	{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
 		NONE, NONE, NONE, NONE} },
 	{}
-- 
1.7.6.GIT

^ permalink raw reply related	[flat|nested] 3+ messages in thread
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2014-11-12 10:30 [U-Boot] [PATCH 2/3] B4860QDS: SGMII related updates Shaveta Leekha
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2014-11-12 10:10 [U-Boot] [PATCH 1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420 Shaveta Leekha
2014-11-12 10:10 ` [U-Boot] [PATCH 2/3] B4860QDS: SGMII related updates Shaveta Leekha

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