Re: [PATCH] drm/i915/bdw: Fix the write setting up the WIZ hashing mode

From: Dave Gordon <david.s.gordon@intel.com>
To: Damien Lespiau <damien.lespiau@intel.com>,
	Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/bdw: Fix the write setting up the WIZ	hashing mode
Date: Mon, 08 Dec 2014 14:17:45 +0000	[thread overview]
Message-ID: <5485B309.50103@intel.com> (raw)
In-Reply-To: <20141208135950.GB4337@strange.ger.corp.intel.com>

On 08/12/14 13:59, Damien Lespiau wrote:
> On Mon, Dec 08, 2014 at 02:33:57PM +0200, Jani Nikula wrote:
>>>  #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
>>>  #define _MASKED_BIT_DISABLE(a) ((a) << 16)
>>> +#define _MASKED_FIELD(value, mask) (((mask) << 16) | (value))
>>
>> Obligatory bikeshed, wouldn't you say _MASKED_BIT_{ENABLE,DISABLE} are
>> special cases of _MASKED_FIELD...? ;)
> 
> That's because we're not just enabling or disabling bits here but
> setting a multi-bits value.
> 
>   _MASKED_FIELD(2 << 4, 0x3 << 4);
> 

So you could

#define	__MASKED_BIT_DISABLE(a)		(__MASKED_FIELD(0, (a)))
#define	__MASKED_BIT_ENABLE(a)		(__MASKED_FIELD((a), (a)))

which I think is what Jani was referring to ...

Bikeshed++: do we care about the double evaluation of (a) in these macros?

.Dave.
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