Re: [PATCH v2] drm/i915/bdw: Fix the write setting up the WIZ hashing mode

From: Dave Gordon <david.s.gordon@intel.com>
To: Daniel Vetter <daniel@ffwll.ch>,
	Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915/bdw: Fix the write setting up the WIZ hashing mode
Date: Mon, 08 Dec 2014 16:50:13 +0000	[thread overview]
Message-ID: <5485D6C5.8000801@intel.com> (raw)
In-Reply-To: <20141208162756.GA27182@phenom.ffwll.local>

On 08/12/14 16:27, Daniel Vetter wrote:
> On Mon, Dec 08, 2014 at 04:22:27PM +0000, Damien Lespiau wrote:
>> I was playing with clang and oh surprise! a warning trigerred by
>> -Wshift-overflow (gcc doesn't have this one):

[snip]

>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 79b4ca5..9deb152 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -739,6 +739,9 @@ static int wa_add(struct drm_i915_private *dev_priv,
>>  #define WA_CLR_BIT_MASKED(addr, mask) \
>>  	WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
>>  
>> +#define WA_SET_FIELD_MASKED(addr, mask, value) \
>> +	WA_REG(addr, _MASKED_FIELD(mask, value), mask)
>> +
>>  #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
>>  #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)

Not your changes, but:

* WA_{SET,CLR}_BIT() above look dubious and don't seem to be used anyway

* dev_priv->workarounds.reg[idx].mask = mask;

The mask field is set but not used in intel_ring_workarounds_emit() or
intel_logical_ring_workarounds_emit(), only in debugfs printout.
And it's redundant since the 'value' incorporates the bit(field) mask
and the new target value into one parameter, hence 3rd parameter of
WA_REG() is surplus and calculating it in WA_{SET,CLR_BIT_MASKED() is
also redundant.

Unless I've missed something?

.Dave.
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