From: David Morrison <dmorrison@invlim.com>
To: qemu-devel@nongnu.org, qemu-trivial@nongnu.org, proljc@gmail.com
Subject: Re: [Qemu-trivial] [PATCH] target-openrisc: bugfixes for debugging with GDB+Qemu on OpenRISC
Date: Mon, 05 Jan 2015 09:59:26 -0800 [thread overview]
Message-ID: <54AAD0FE.2090902@invlim.com> (raw)
In-Reply-To: <1418862393-10691-1-git-send-email-dmorrison@invlim.com>
ping
On 12/17/2014 04:26 PM, David Morrison wrote:
> This patch fixes two bugs in Qemu for OpenRISC, and enables more
> functionality from or1k-elf-gdb:
>
> 1) Fixed the decoding of "system" instructions (starting with 0x2)
> in dec_sys() in translate.c. In particular, the l.trap instruction
> is now correctly decoded, which enables for singlestepping and
> breakpoints to be set in GDB.
>
> 2) Fixed a memory read error when debugging kernels inside Qemu and
> the OpenRISC MMU is enabled
>
> Signed-off-by: David R. Morrison <dmorrison@invlim.com>
> ---
> target-openrisc/cpu.h | 1 +
> target-openrisc/mmu.c | 2 +-
> target-openrisc/translate.c | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
> index 69b96c6..6b08af6 100644
> --- a/target-openrisc/cpu.h
> +++ b/target-openrisc/cpu.h
> @@ -20,6 +20,7 @@
> #ifndef CPU_OPENRISC_H
> #define CPU_OPENRISC_H
>
> +#define TARGET_HAS_ICE
> #define TARGET_LONG_BITS 32
> #define ELF_MACHINE EM_OPENRISC
>
> diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
> index 750a936..bbd05f1 100644
> --- a/target-openrisc/mmu.c
> +++ b/target-openrisc/mmu.c
> @@ -219,7 +219,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> hwaddr phys_addr;
> int prot;
>
> - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
> + if (cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0)) {
> return -1;
> }
>
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index 407bd97..d36278f 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -1320,7 +1320,7 @@ static void dec_sys(DisasContext *dc, uint32_t insn)
> #ifdef OPENRISC_DISAS
> uint32_t K16;
> #endif
> - op0 = extract32(insn, 16, 8);
> + op0 = extract32(insn, 16, 10);
> #ifdef OPENRISC_DISAS
> K16 = extract32(insn, 0, 16);
> #endif
>
--
David R. Morrison, PhD
Inverse Limit
dmorrison@invlim.com
+1-217-417-9445
WARNING: multiple messages have this Message-ID (diff)
From: David Morrison <dmorrison@invlim.com>
To: qemu-devel@nongnu.org, qemu-trivial@nongnu.org, proljc@gmail.com
Subject: Re: [Qemu-devel] [PATCH] target-openrisc: bugfixes for debugging with GDB+Qemu on OpenRISC
Date: Mon, 05 Jan 2015 09:59:26 -0800 [thread overview]
Message-ID: <54AAD0FE.2090902@invlim.com> (raw)
In-Reply-To: <1418862393-10691-1-git-send-email-dmorrison@invlim.com>
ping
On 12/17/2014 04:26 PM, David Morrison wrote:
> This patch fixes two bugs in Qemu for OpenRISC, and enables more
> functionality from or1k-elf-gdb:
>
> 1) Fixed the decoding of "system" instructions (starting with 0x2)
> in dec_sys() in translate.c. In particular, the l.trap instruction
> is now correctly decoded, which enables for singlestepping and
> breakpoints to be set in GDB.
>
> 2) Fixed a memory read error when debugging kernels inside Qemu and
> the OpenRISC MMU is enabled
>
> Signed-off-by: David R. Morrison <dmorrison@invlim.com>
> ---
> target-openrisc/cpu.h | 1 +
> target-openrisc/mmu.c | 2 +-
> target-openrisc/translate.c | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
> index 69b96c6..6b08af6 100644
> --- a/target-openrisc/cpu.h
> +++ b/target-openrisc/cpu.h
> @@ -20,6 +20,7 @@
> #ifndef CPU_OPENRISC_H
> #define CPU_OPENRISC_H
>
> +#define TARGET_HAS_ICE
> #define TARGET_LONG_BITS 32
> #define ELF_MACHINE EM_OPENRISC
>
> diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
> index 750a936..bbd05f1 100644
> --- a/target-openrisc/mmu.c
> +++ b/target-openrisc/mmu.c
> @@ -219,7 +219,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> hwaddr phys_addr;
> int prot;
>
> - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
> + if (cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0)) {
> return -1;
> }
>
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index 407bd97..d36278f 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -1320,7 +1320,7 @@ static void dec_sys(DisasContext *dc, uint32_t insn)
> #ifdef OPENRISC_DISAS
> uint32_t K16;
> #endif
> - op0 = extract32(insn, 16, 8);
> + op0 = extract32(insn, 16, 10);
> #ifdef OPENRISC_DISAS
> K16 = extract32(insn, 0, 16);
> #endif
>
--
David R. Morrison, PhD
Inverse Limit
dmorrison@invlim.com
+1-217-417-9445
next prev parent reply other threads:[~2015-01-05 17:59 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-18 0:26 [Qemu-trivial] [PATCH] target-openrisc: bugfixes for debugging with GDB+Qemu on OpenRISC David Morrison
2014-12-18 0:26 ` [Qemu-devel] " David Morrison
2015-01-05 17:59 ` David Morrison [this message]
2015-01-05 17:59 ` David Morrison
2015-01-05 18:15 ` [Qemu-trivial] " Peter Maydell
2015-01-05 18:15 ` Peter Maydell
2015-01-05 18:33 ` [Qemu-trivial] " Peter Maydell
2015-01-05 18:33 ` Peter Maydell
2015-01-05 18:41 ` [Qemu-trivial] " David Morrison
2015-01-05 18:41 ` David Morrison
2015-01-05 18:48 ` [Qemu-trivial] " Peter Maydell
2015-01-05 18:48 ` Peter Maydell
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