[PATCH] MIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controller

[PATCH] MIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controller

[Joshua Kinard]

From: Joshua Kinard <kumba@gentoo.org>

On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI
buses attached to the Xtalk bus.  The current code will stop counting PCI buses
after it finds the first one.  If one installs the optional PCI cardcage
("shoebox") into these systems, because of the order of the Xtalk widgets, the
current PCI code will find the cardcage first, and fail to detect the BaseIO
PCI devices, which are on a higher Xtalk widget ID.

This patch adds the hooks needed for resolving this issue in the IP27 PCI code
(in a later patch).

Verified on both an SGI Onyx2 and an SGI Octane.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
---
 arch/mips/include/asm/pci.h        |    2 ++
 arch/mips/include/asm/pci/bridge.h |    1 +
 arch/mips/pci/pci.c                |    5 ++++-
 3 files changed, 7 insertions(+), 1 deletion(-)

Ralf,

  I have the needed IP27 changes, but I tied them up with some cleanups to the
Xtalk code to make it more centralized so I could remove duplicate code from
the Octane's patches.  I've still gotta fiddle with that code some more and
remove the debug bits, but this change should be safe to go in by itself, as
it's a prerequisite.  I'll probably send the IP27 bits in along with the IOC3
stuff, because IP27 seems to be very flakey (at least my Onyx2 was) with the
in-tree IOC3 bits.  Most common was requiring several reboots to properly
detect the MAC address.  Under the metadriver, it detects things fine.


linux-mips-pci-busn.patch
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 6952962..4610c9f 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -35,6 +35,8 @@ struct pci_controller {
 	struct resource *io_resource;
 	unsigned long io_offset;
 	unsigned long io_map_base;
+	struct resource *busn_resource;
+	unsigned long busn_offset;
 
 	unsigned int index;
 	/* For compatibility with current (as of July 2003) pciutils
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index af2c8a3..8d7a63b 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -835,6 +835,7 @@ struct bridge_controller {
 	struct pci_controller	pc;
 	struct resource		mem;
 	struct resource		io;
+	struct resource		busn;
 	bridge_t		*base;
 	nasid_t			nasid;
 	unsigned int		widget_id;
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 1bf60b1..0e3f437 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -91,7 +91,10 @@ static void pcibios_scanbus(struct pci_controller *hose)
 
 	pci_add_resource_offset(&resources,
 				hose->mem_resource, hose->mem_offset);
-	pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
+	pci_add_resource_offset(&resources,
+				hose->io_resource, hose->io_offset);
+	pci_add_resource_offset(&resources,
+				hose->busn_resource, hose->busn_offset);
 	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
 				&resources);
 	if (!bus)

Re: [PATCH] MIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controller

[Ralf Baechle]

On Mon, Jan 19, 2015 at 04:19:20AM -0500, Joshua Kinard wrote:

> From: Joshua Kinard <kumba@gentoo.org>
> 
> On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI
> buses attached to the Xtalk bus.  The current code will stop counting PCI buses
> after it finds the first one.  If one installs the optional PCI cardcage
> ("shoebox") into these systems, because of the order of the Xtalk widgets, the
> current PCI code will find the cardcage first, and fail to detect the BaseIO
> PCI devices, which are on a higher Xtalk widget ID.
> 
> This patch adds the hooks needed for resolving this issue in the IP27 PCI code
> (in a later patch).
> 
> Verified on both an SGI Onyx2 and an SGI Octane.
> 
> Signed-off-by: Joshua Kinard <kumba@gentoo.org>
> ---
>  arch/mips/include/asm/pci.h        |    2 ++
>  arch/mips/include/asm/pci/bridge.h |    1 +
>  arch/mips/pci/pci.c                |    5 ++++-
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> Ralf,
> 
>   I have the needed IP27 changes, but I tied them up with some cleanups to the
> Xtalk code to make it more centralized so I could remove duplicate code from
> the Octane's patches.  I've still gotta fiddle with that code some more and
> remove the debug bits, but this change should be safe to go in by itself, as
> it's a prerequisite.  I'll probably send the IP27 bits in along with the IOC3
> stuff, because IP27 seems to be very flakey (at least my Onyx2 was) with the
> in-tree IOC3 bits.  Most common was requiring several reboots to properly
> detect the MAC address.  Under the metadriver, it detects things fine.

There's a long-standing defect in the IOC3 code resulting in bad timing
for the 1-Wire bus driver.  The reason is that some bitfield is incorrectly
sized resulting in overflow.

As for the patch itself - everybody had their fair chance at yelling, nobody
did so I queued it up for 4.1.

  Ralf