From: sergei.shtylyov@cogentembedded.com (Sergei Shtylyov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
Date: Tue, 27 Jan 2015 13:24:29 +0300 [thread overview]
Message-ID: <54C7675D.8000204@cogentembedded.com> (raw)
In-Reply-To: <1422338006-3371-1-git-send-email-wenyou.yang@atmel.com>
Hello.
On 1/27/2015 8:53 AM, Wenyou Yang wrote:
> From: Peter Rosin <peda@axentia.se>
> The DDRSDR controller fails miserably to put LPDDR1 memories in
> self-refresh. Force the controller to think it has DDR2 memories
> during the self-refresh period, as the DDR2 self-refresh spec is
> equivalent to LPDDR1, and is correctly implemented in the
> controller.
> Assume that the second controller has the same fault, but that is
> untested.
> Signed-off-by: Peter Rosin <peda@axentia.se>
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/mach-at91/pm_slowclock.S | 43 +++++++++++++++++++++++++++++++-----
> include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> 2 files changed, 39 insertions(+), 6 deletions(-)
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index e2bfaf5..1155217 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
[...]
> @@ -108,14 +118,26 @@ ddr_sr_enable:
>
> /* figure out if we use the second ram controller */
> cmp ramc1, #0
> - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> - strne tmp2, .saved_sam9_lpr1
> - bicne tmp2, #AT91_DDRSDRC_LPCB
> - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> + beq ddr_no_2nd_ctrl
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + str tmp2, .saved_sam9_mdr1
> + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
Didn't you forget ~? Either that, or ~ above is not needed, I think.
> + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> + str tmp2, .saved_sam9_lpr1
> + bic tmp2, #AT91_DDRSDRC_LPCB
Didn't you forget ~? And isn't it 3-operand instruction (as seen in the
above code)?
> + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
Only 2 operands?
[...]
WBR, Sergei
WARNING: multiple messages have this Message-ID (diff)
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Wenyou Yang <wenyou.yang@atmel.com>,
nicolas.ferre@atmel.com, linux@arm.linux.org.uk
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
alexandre.belloni@free-electrons.com,
sylvain.rochet@finsecur.com, peda@axentia.se, linux@maxim.org.za
Subject: Re: [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
Date: Tue, 27 Jan 2015 13:24:29 +0300 [thread overview]
Message-ID: <54C7675D.8000204@cogentembedded.com> (raw)
In-Reply-To: <1422338006-3371-1-git-send-email-wenyou.yang@atmel.com>
Hello.
On 1/27/2015 8:53 AM, Wenyou Yang wrote:
> From: Peter Rosin <peda@axentia.se>
> The DDRSDR controller fails miserably to put LPDDR1 memories in
> self-refresh. Force the controller to think it has DDR2 memories
> during the self-refresh period, as the DDR2 self-refresh spec is
> equivalent to LPDDR1, and is correctly implemented in the
> controller.
> Assume that the second controller has the same fault, but that is
> untested.
> Signed-off-by: Peter Rosin <peda@axentia.se>
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/mach-at91/pm_slowclock.S | 43 +++++++++++++++++++++++++++++++-----
> include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> 2 files changed, 39 insertions(+), 6 deletions(-)
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index e2bfaf5..1155217 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
[...]
> @@ -108,14 +118,26 @@ ddr_sr_enable:
>
> /* figure out if we use the second ram controller */
> cmp ramc1, #0
> - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> - strne tmp2, .saved_sam9_lpr1
> - bicne tmp2, #AT91_DDRSDRC_LPCB
> - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> + beq ddr_no_2nd_ctrl
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + str tmp2, .saved_sam9_mdr1
> + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
Didn't you forget ~? Either that, or ~ above is not needed, I think.
> + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> + str tmp2, .saved_sam9_lpr1
> + bic tmp2, #AT91_DDRSDRC_LPCB
Didn't you forget ~? And isn't it 3-operand instruction (as seen in the
above code)?
> + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
Only 2 operands?
[...]
WBR, Sergei
next prev parent reply other threads:[~2015-01-27 10:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-27 5:50 [PATCH v3 00/13] AT91 pm cleanup for 3.20 Wenyou Yang
2015-01-27 5:50 ` Wenyou Yang
2015-01-27 5:51 ` [PATCH v3 01/13] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts Wenyou Yang
2015-01-27 5:51 ` Wenyou Yang
2015-01-27 5:52 ` [PATCH v3 02/13] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode Wenyou Yang
2015-01-27 5:52 ` Wenyou Yang
2015-01-27 5:53 ` [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories Wenyou Yang
2015-01-27 5:53 ` Wenyou Yang
2015-01-27 10:24 ` Sergei Shtylyov [this message]
2015-01-27 10:24 ` Sergei Shtylyov
2015-01-27 12:14 ` Peter Rosin
2015-01-27 12:14 ` Peter Rosin
2015-01-27 21:55 ` Peter Rosin
2015-01-27 21:55 ` Peter Rosin
2015-01-27 22:43 ` Russell King - ARM Linux
2015-01-27 22:43 ` Russell King - ARM Linux
2015-01-27 5:54 ` [PATCH v3 04/13] pm: at91: pm_slowclock: remove the unused code related with SLOWDOWN_MASTER_CLOCK Wenyou Yang
2015-01-27 5:54 ` Wenyou Yang
2015-01-27 5:55 ` [PATCH v3 05/13] pm: at91: move the copying the sram function to the sram initializationi phase Wenyou Yang
2015-01-27 5:55 ` Wenyou Yang
2015-01-27 5:56 ` [PATCH v3 06/13] ARM: at91: move select SRAM to ARCH_AT91 Wenyou Yang
2015-01-27 5:56 ` Wenyou Yang
2015-01-27 5:57 ` [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK Wenyou Yang
2015-01-27 5:57 ` Wenyou Yang
2015-01-27 9:55 ` Sylvain Rochet
2015-01-27 9:55 ` Sylvain Rochet
2015-01-27 10:07 ` Alexandre Belloni
2015-01-27 10:07 ` Alexandre Belloni
2015-01-27 10:13 ` Sylvain Rochet
2015-01-27 10:13 ` Sylvain Rochet
2015-01-27 5:58 ` [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode Wenyou Yang
2015-01-27 5:58 ` Wenyou Yang
2015-01-27 10:08 ` Sylvain Rochet
2015-01-27 10:08 ` Sylvain Rochet
2015-01-27 10:11 ` Yang, Wenyou
2015-01-27 10:11 ` Yang, Wenyou
2015-01-27 5:59 ` [PATCH v3 09/13] pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S Wenyou Yang
2015-01-27 5:59 ` Wenyou Yang
2015-01-27 5:59 ` [PATCH v3 10/13] pm: at91: rename function name: at91_slow_clock()-->at91_pm_suspend_sram_fn Wenyou Yang
2015-01-27 5:59 ` Wenyou Yang
2015-01-27 6:00 ` [PATCH v3 11/13] pm: at91: remove the at91_xxx_standby() function definitions in the pm.h Wenyou Yang
2015-01-27 6:00 ` Wenyou Yang
2015-01-27 6:01 ` [PATCH v3 12/13] pm: at91: setup: remove the struct ramc_ids .data at91_xxx_standby members Wenyou Yang
2015-01-27 6:01 ` Wenyou Yang
2015-01-27 6:01 ` [PATCH v3 13/13] pm: at91: amend the pm_suspend entry for at91_cpuidle_device Wenyou Yang
2015-01-27 6:01 ` Wenyou Yang
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