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* [PATCH v2 1/3] MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation
@ 2015-01-29 15:06 Manuel Lauss
  2015-01-29 15:06 ` [PATCH v2 2/3] MIPS: Alchemy: preset loops_per_jiffy based on CPU clock Manuel Lauss
  2015-01-29 15:06 ` [PATCH v2 3/3] MIPS: Alchemy: remove declaration for set_cpuspec Manuel Lauss
  0 siblings, 2 replies; 4+ messages in thread
From: Manuel Lauss @ 2015-01-29 15:06 UTC (permalink / raw)
  To: Linux-MIPS; +Cc: Ralf Baechle, Manuel Lauss

The Au1000 and Au1500 calculate the LRCLK a bit differently than
newer models: a single bit in MEM_STCFG0 selects if pclk is divided
by 4 or 5.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
---
v2: address Sergei's comments.

 arch/mips/alchemy/common/clock.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 48a9dfc..f8f54b8 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -315,17 +315,26 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
 
 /* lrclk: external synchronous static bus clock ***********************/
 
-static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
+static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
 {
-	/* MEM_STCFG0[15:13] = divisor.
+	/* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
+	 * otherwise lrclk=pclk/4.
+	 * All other variants: MEM_STCFG0[15:13] = divisor.
 	 * L/RCLK = periph_clk / (divisor + 1)
 	 * On Au1000, Au1500, Au1100 it's called LCLK,
 	 * on later models it's called RCLK, but it's the same thing.
 	 */
 	struct clk *c;
-	unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
+	unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
 
-	v = (v & 7) + 1;
+	switch (t) {
+	case ALCHEMY_CPU_AU1000:
+	case ALCHEMY_CPU_AU1500:
+		v = 4 + ((v >> 11) & 1);
+		break;
+	default:	/* all other models */
+		v = ((v >> 13) & 7) + 1;
+	}
 	c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
 				      pn, 0, 1, v);
 	if (!IS_ERR(c))
@@ -1060,7 +1069,7 @@ static int __init alchemy_clk_init(void)
 	ERRCK(c)
 
 	/* L/RCLK: external static bus clock for synchronous mode */
-	c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
+	c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
 	ERRCK(c)
 
 	/* Frequency dividers 0-5 */
-- 
2.2.2

^ permalink raw reply related	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2015-01-29 16:33 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-01-29 15:06 [PATCH v2 1/3] MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation Manuel Lauss
2015-01-29 15:06 ` [PATCH v2 2/3] MIPS: Alchemy: preset loops_per_jiffy based on CPU clock Manuel Lauss
2015-01-29 16:33   ` Sergei Shtylyov
2015-01-29 15:06 ` [PATCH v2 3/3] MIPS: Alchemy: remove declaration for set_cpuspec Manuel Lauss

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