[Qemu-devel] Intel X86 hardware transactional memory

[Qemu-devel] Intel X86 hardware transactional memory

[Xin Tong]

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If i want to implement Intel X86 hardware transactional memory (HTM) in
QEMU. what would be a good way to track the memory accesses.

I think one possible way is to clear the software tlb on entry to the
transaction and disable (not install any translations) the software TLB
till the end of the transaction.

In the softmmu helper functions, the memory addresses as well as value can
then be tracked in a hashtable and committed to system memory once the
transaction is ready to be committed.

Thanks
Trent

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Re: [Qemu-devel] Intel X86 hardware transactional memory

[Patrick Williams III]

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Re: [Qemu-devel] Intel X86 hardware transactional memory

[Richard Henderson]

On 02/04/2015 09:09 PM, Patrick Williams III wrote:
>>I think one possible way is to clear the software tlb on entry to the
>>transaction and disable (not install any translations) the software
>>TLB till the end of the transaction. 
>>In the softmmu helper functions, the memory addresses as well as
>>value can then be tracked in a hashtable and committed to system
>>memory once the transaction is ready to be committed.
> 
> I believe the transaction conflicts are handled post-translation by the cache
> coherency protocol.  Trying to store the pre-translation address isn't
> sufficient for conflict resolution.
> 
> Consider two virtual addresses that point to the same physical address.  One
> thread uses the first virtual address in a transaction; another thread writes
> to the second virtual address while the transaction is going on.  This should
> cause the transaction to fail because the same physical address was involved.

That's not really relevant.  The important part is that no TLB hits are made
within TCG, so that we always use the softmmu helpers.

Incidentally, that's also accomplished by bits such as TLB_NOTDIRTY.  We could
add another bit so that pages referenced by TM don't need to be fetched out of
the page tables every time.


r~

Re: [Qemu-devel] Intel X86 hardware transactional memory

[Xin Tong]

On Thu, Feb 5, 2015 at 5:52 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 02/04/2015 09:09 PM, Patrick Williams III wrote:
>>>I think one possible way is to clear the software tlb on entry to the
>>>transaction and disable (not install any translations) the software
>>>TLB till the end of the transaction.
>>>In the softmmu helper functions, the memory addresses as well as
>>>value can then be tracked in a hashtable and committed to system
>>>memory once the transaction is ready to be committed.
>>
>> I believe the transaction conflicts are handled post-translation by the cache
>> coherency protocol.  Trying to store the pre-translation address isn't
>> sufficient for conflict resolution.
>>
>> Consider two virtual addresses that point to the same physical address.  One
>> thread uses the first virtual address in a transaction; another thread writes
>> to the second virtual address while the transaction is going on.  This should
>> cause the transaction to fail because the same physical address was involved.
>
> That's not really relevant.  The important part is that no TLB hits are made
> within TCG, so that we always use the softmmu helpers.
>
> Incidentally, that's also accomplished by bits such as TLB_NOTDIRTY.  We could
> add another bit so that pages referenced by TM don't need to be fetched out of
> the page tables every time.
>
>
> r~

I agree conflict detection should be down on physical addresses. we do
have physical addresses in the softmmu helpers. On a side note, is
there a plan to be provide a set of functionalities in QEMU to make
implementing transactional memory easier ?

Xin

Re: [Qemu-devel] Intel X86 hardware transactional memory

[Richard Henderson]

On 02/05/2015 07:36 PM, Xin Tong wrote:
> I agree conflict detection should be down on physical addresses. we do
> have physical addresses in the softmmu helpers. On a side note, is
> there a plan to be provide a set of functionalities in QEMU to make
> implementing transactional memory easier ?

No one is working on it that I know of.


r~

Re: [Qemu-devel] Intel X86 hardware transactional memory

[Peter Maydell]

On 5 February 2015 at 05:09, Patrick Williams III <iawillia@us.ibm.com> wrote:
> Consider two virtual addresses that point to the same physical address.  One
> thread uses the first virtual address in a transaction; another thread
> writes to the second virtual address while the transaction is going on.
> This should cause the transaction to fail because the same physical address
> was involved.

Incidentally comparison against physical addresses, not virtual
addresses, is also the correct semantics for ARM load/store
exclusive instructions. At the moment we implement those with
a mechanism that is completely architecturally wrong but happens
to work for the stereotypical uses of those insns. If we ever
wanted to do it right then we'd need some way of catching
"some other CPU did a write to the physaddr we have an exclusive
lock for".

[Somebody pointed this out to me on IRC last night.]

-- PMM