* [PATCH v3 0/8] arm64: Add the support for new Exynos5433 SoC
@ 2015-02-12 6:55 ` Chanwoo Choi
0 siblings, 0 replies; 25+ messages in thread
From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw)
To: linux-samsung-soc, linux-kernel
Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas,
will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim,
jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset is based on linux-samsung.git (branch: for-next).
Depends on:
- Exynos5433 clock controller patch-set[1][2] was merged by Sylwester Nawrocki,
(http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/, branch:for-v3.20/clk/next)
- Exynos5433 UART patch[4] was merged by GregKH.
[1] [PATCH v5 00/13] clk: samsung: Add the support for exynos5433 clocks
- https://lkml.org/lkml/2015/2/2/368
[2] [PATCH v3 0/9] clk: samsung: Add clocks for remaining domains of Exynos5433
- https://lkml.org/lkml/2015/2/2/784
[3] [PATCHv2] pinctrl: exynos: Add support for Exynos543
- https://lkml.org/lkml/2014/12/2/207
[4] serial: samsung: Add the support for Exynos5433 SoC
- http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=31ec77aca72ee5920ed3ec3d047734dc0bc43342
Changelog:
Changes from v2:
(https://lkml.org/lkml/2014/12/2/134)
- Exynos5444 DTS modification
: Fix the range of GICC memory map (0x1000 -> 0x2000)
: Fix address space of 'range' property under 'soc' node
: Add ADMA / I2S dt node for sound playback/capture
- Select ARM_AMBA/ARM_GIC/HAVE_S3C_RTC for Exynos5433 in arch/arm64/Kconfig
- Send separate patch-set for Exynos5433 clock controller[1][2] and pinctrl[3]
Changes from v1:
(https://lkml.org/lkml/2014/11/27/92)
- Merge two patches (patch2, patch3) to solve incomplete description
- Exynos5433 Clock driver
: Fix wrong register and code clean by using space instead of tab
: Add CLK_IGNORE_UNUSED flag to pclk_sysreg_* clock for accessing system control register
: Remove duplicate definition on the patch for CMU_BUS{0|1|2} domain
- Exynos5433 SoC DTS
: Remove un-supported properties of arch_timer
: Remove 'clock-frequency' property from 'cpus' dt node
: Fix interrupt type from edge rising triggering to level high triggering
because Cortex-A53/A57 use level triggering.
: Fix defult address-size/size-celss from 1 to 2 because Exynos5433 is 64-bit SoC
: Modify 'fin_pll' dt node to remove un-needed and ugly code
: Move 'chipid' dt node under 'soc'
: Use lowercase on all case in exynos5433.dtsi
: Add PSCI dt node for secondary cpu boot
: Add 'samsung,exynos5433' compatible to MCT dt node
- Divide pinctrl patch from this patchset
- Add new following patches:
: clocksource: exynos_mct: Add the support for Exynos 64bit SoC
: arm64: Enable Exynos5433 SoC in the defconfig
Chanwoo Choi (5):
arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support
arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC
arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433
arm64: dts: exynos: Add PMU dt node for Exynos5433
arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC
Inha Song (2):
arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC
arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC
Jaehoon Chung (1):
arm64: dts: exynos: Add MSHC dt node for Exynos5433
.../devicetree/bindings/arm/samsung/pmu.txt | 1 +
arch/arm64/Kconfig | 13 +
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 ++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 911 +++++++++++++++++++++
4 files changed, 1623 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
--
1.8.5.5
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v3 0/8] arm64: Add the support for new Exynos5433 SoC @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process. This patchset is based on linux-samsung.git (branch: for-next). Depends on: - Exynos5433 clock controller patch-set[1][2] was merged by Sylwester Nawrocki, (http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/, branch:for-v3.20/clk/next) - Exynos5433 UART patch[4] was merged by GregKH. [1] [PATCH v5 00/13] clk: samsung: Add the support for exynos5433 clocks - https://lkml.org/lkml/2015/2/2/368 [2] [PATCH v3 0/9] clk: samsung: Add clocks for remaining domains of Exynos5433 - https://lkml.org/lkml/2015/2/2/784 [3] [PATCHv2] pinctrl: exynos: Add support for Exynos543 - https://lkml.org/lkml/2014/12/2/207 [4] serial: samsung: Add the support for Exynos5433 SoC - http://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=31ec77aca72ee5920ed3ec3d047734dc0bc43342 Changelog: Changes from v2: (https://lkml.org/lkml/2014/12/2/134) - Exynos5444 DTS modification : Fix the range of GICC memory map (0x1000 -> 0x2000) : Fix address space of 'range' property under 'soc' node : Add ADMA / I2S dt node for sound playback/capture - Select ARM_AMBA/ARM_GIC/HAVE_S3C_RTC for Exynos5433 in arch/arm64/Kconfig - Send separate patch-set for Exynos5433 clock controller[1][2] and pinctrl[3] Changes from v1: (https://lkml.org/lkml/2014/11/27/92) - Merge two patches (patch2, patch3) to solve incomplete description - Exynos5433 Clock driver : Fix wrong register and code clean by using space instead of tab : Add CLK_IGNORE_UNUSED flag to pclk_sysreg_* clock for accessing system control register : Remove duplicate definition on the patch for CMU_BUS{0|1|2} domain - Exynos5433 SoC DTS : Remove un-supported properties of arch_timer : Remove 'clock-frequency' property from 'cpus' dt node : Fix interrupt type from edge rising triggering to level high triggering because Cortex-A53/A57 use level triggering. : Fix defult address-size/size-celss from 1 to 2 because Exynos5433 is 64-bit SoC : Modify 'fin_pll' dt node to remove un-needed and ugly code : Move 'chipid' dt node under 'soc' : Use lowercase on all case in exynos5433.dtsi : Add PSCI dt node for secondary cpu boot : Add 'samsung,exynos5433' compatible to MCT dt node - Divide pinctrl patch from this patchset - Add new following patches: : clocksource: exynos_mct: Add the support for Exynos 64bit SoC : arm64: Enable Exynos5433 SoC in the defconfig Chanwoo Choi (5): arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433 arm64: dts: exynos: Add PMU dt node for Exynos5433 arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC Inha Song (2): arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC Jaehoon Chung (1): arm64: dts: exynos: Add MSHC dt node for Exynos5433 .../devicetree/bindings/arm/samsung/pmu.txt | 1 + arch/arm64/Kconfig | 13 + arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 ++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 911 +++++++++++++++++++++ 4 files changed, 1623 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi -- 1.8.5.5 ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support 2015-02-12 6:55 ` Chanwoo Choi @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 15e8e74..4fc08d1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -153,6 +153,19 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool "ARMv8 based Samsung Exynos5433" + select ARCH_EXYNOS + select ARM_AMBA + select ARM_GIC + select COMMON_CLK_SAMSUNG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos5433 SoC. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 15e8e74..4fc08d1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -153,6 +153,19 @@ config ARCH_EXYNOS help This enables support for Samsung Exynos SoC family +config ARCH_EXYNOS5433 + bool "ARMv8 based Samsung Exynos5433" + select ARCH_EXYNOS + select ARM_AMBA + select ARM_GIC + select COMMON_CLK_SAMSUNG + select HAVE_S3C_RTC if RTC_CLASS + select PINCTRL + select PINCTRL_EXYNOS + + help + This enables support for Samsung Exynos5433 SoC family + config ARCH_EXYNOS7 bool "ARMv8 based Samsung Exynos7" select ARCH_EXYNOS -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
[parent not found: <1423724158-23632-2-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>]
* Re: [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support 2015-02-12 6:55 ` Chanwoo Choi (?) @ 2015-02-12 11:02 ` Catalin Marinas -1 siblings, 0 replies; 25+ messages in thread From: Catalin Marinas @ 2015-02-12 11:02 UTC (permalink / raw) To: Chanwoo Choi Cc: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8, jh80.chung-Sze3O3UU22JBDgjK7y7TUQ, arnd-r2nGTMty4D4, marc.zyngier-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8, a.kesavan-Sze3O3UU22JBDgjK7y7TUQ, inki.dae-Sze3O3UU22JBDgjK7y7TUQ, sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA, kgene-DgEjT+Ai2ygdnm+yROfE0A, sangbae90.lee-Sze3O3UU22JBDgjK7y7TUQ, olof-nZhT3qVonbNeoWH0uzbU5w, chanho61.park-Sze3O3UU22JBDgjK7y7TUQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Thu, Feb 12, 2015 at 03:55:51PM +0900, Chanwoo Choi wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 15e8e74..4fc08d1 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -153,6 +153,19 @@ config ARCH_EXYNOS > help > This enables support for Samsung Exynos SoC family > > +config ARCH_EXYNOS5433 > + bool "ARMv8 based Samsung Exynos5433" > + select ARCH_EXYNOS > + select ARM_AMBA > + select ARM_GIC ARM_GIC and ARM_AMBA are already selected by the top ARM64 config. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support @ 2015-02-12 11:02 ` Catalin Marinas 0 siblings, 0 replies; 25+ messages in thread From: Catalin Marinas @ 2015-02-12 11:02 UTC (permalink / raw) To: Chanwoo Choi Cc: linux-samsung-soc, linux-kernel, mark.rutland, jh80.chung, arnd, marc.zyngier, will.deacon, a.kesavan, inki.dae, sw0312.kim, devicetree, kgene, sangbae90.lee, olof, chanho61.park, linux-arm-kernel On Thu, Feb 12, 2015 at 03:55:51PM +0900, Chanwoo Choi wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 15e8e74..4fc08d1 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -153,6 +153,19 @@ config ARCH_EXYNOS > help > This enables support for Samsung Exynos SoC family > > +config ARCH_EXYNOS5433 > + bool "ARMv8 based Samsung Exynos5433" > + select ARCH_EXYNOS > + select ARM_AMBA > + select ARM_GIC ARM_GIC and ARM_AMBA are already selected by the top ARM64 config. -- Catalin ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support @ 2015-02-12 11:02 ` Catalin Marinas 0 siblings, 0 replies; 25+ messages in thread From: Catalin Marinas @ 2015-02-12 11:02 UTC (permalink / raw) To: linux-arm-kernel On Thu, Feb 12, 2015 at 03:55:51PM +0900, Chanwoo Choi wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 15e8e74..4fc08d1 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -153,6 +153,19 @@ config ARCH_EXYNOS > help > This enables support for Samsung Exynos SoC family > > +config ARCH_EXYNOS5433 > + bool "ARMv8 based Samsung Exynos5433" > + select ARCH_EXYNOS > + select ARM_AMBA > + select ARM_GIC ARM_GIC and ARM_AMBA are already selected by the top ARM64 config. -- Catalin ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support 2015-02-12 11:02 ` Catalin Marinas @ 2015-02-12 11:03 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 11:03 UTC (permalink / raw) To: Catalin Marinas Cc: linux-samsung-soc, linux-kernel, mark.rutland, jh80.chung, arnd, marc.zyngier, will.deacon, a.kesavan, inki.dae, sw0312.kim, devicetree, kgene, sangbae90.lee, olof, chanho61.park, linux-arm-kernel Hi Catalin, On 02/12/2015 08:02 PM, Catalin Marinas wrote: > On Thu, Feb 12, 2015 at 03:55:51PM +0900, Chanwoo Choi wrote: >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 15e8e74..4fc08d1 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -153,6 +153,19 @@ config ARCH_EXYNOS >> help >> This enables support for Samsung Exynos SoC family >> >> +config ARCH_EXYNOS5433 >> + bool "ARMv8 based Samsung Exynos5433" >> + select ARCH_EXYNOS >> + select ARM_AMBA >> + select ARM_GIC > > ARM_GIC and ARM_AMBA are already selected by the top ARM64 config. > OK, I'll remove two configurations. Thanks, Chanwoo Choi ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support @ 2015-02-12 11:03 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 11:03 UTC (permalink / raw) To: linux-arm-kernel Hi Catalin, On 02/12/2015 08:02 PM, Catalin Marinas wrote: > On Thu, Feb 12, 2015 at 03:55:51PM +0900, Chanwoo Choi wrote: >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 15e8e74..4fc08d1 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -153,6 +153,19 @@ config ARCH_EXYNOS >> help >> This enables support for Samsung Exynos SoC family >> >> +config ARCH_EXYNOS5433 >> + bool "ARMv8 based Samsung Exynos5433" >> + select ARCH_EXYNOS >> + select ARM_AMBA >> + select ARM_GIC > > ARM_GIC and ARM_AMBA are already selected by the top ARM64 config. > OK, I'll remove two configurations. Thanks, Chanwoo Choi ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 2/8] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC 2015-02-12 6:55 ` Chanwoo Choi @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following dt node to support Exynos5433 SoC: 1. Octa core for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Support PSCI v0.1 2. clock controller node: - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. pinctrl node for GPIO: - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. HS (High-Speed) I2C device 5. Serial device 6. ARCH timer (arm,armv8-timer) 7. Interrupt controller (arm,gic-400) Cc: Kukjin Kim <kgene@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 696 ++++++++++++++++++++ 2 files changed, 1394 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi new file mode 100644 index 0000000..81fe925 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -0,0 +1,698 @@ +/* + * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_aud { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", + "gpz0-4", "gpz0-5", "gpz0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_cpif { + gpv6: gpv6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_ese { + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_finger { + gpd5: gpd5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c6_bus: hs-i2c6-bus { + samsung,pins = "gpd5-3", "gpd5-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + +}; + +&pinctrl_fsys { + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr4: gpr4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr0: gpr0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr1: gpr1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr2: gpr2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr3: gpr3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + sd0_clk: sd0-clk { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpr0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpr0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_qrdy: sd0-qrdy { + samsung,pins = "gpr0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpr1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpr2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpr2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpr3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + pcie_bus: pcie_bus { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpr4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpr4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpr4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk_output: sd2-clk-output { + samsung,pins = "gpr4-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd_output: sd2-cmd-output { + samsung,pins = "gpr4-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; +}; + +&pinctrl_imem { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_nfc { + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c4_bus: hs-i2c4-bus { + samsung,pins = "gpj0-1", "gpj0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + +}; + +&pinctrl_peric { + gpv7: gpv7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd4: gpd4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd8: gpd8 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd6: gpd6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd7: gpd7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c8_bus: hs-i2c8-bus { + samsung,pins = "gpb0-1", "gpb0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c9_bus: hs-i2c9-bus { + samsung,pins = "gpb0-3", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpd4-3", "gpd4-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin0: fimc-is-spi-pin0 { + samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin1: fimc-is-spi-pin1 { + samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_bus: uart0-bus { + samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c2_bus: hs-i2c2-bus { + samsung,pins = "gpd0-3", "gpd0-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_bus: uart2-bus { + samsung,pins = "gpd1-5", "gpd1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart1_bus: uart1-bus { + samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c3_bus: hs-i2c3-bus { + samsung,pins = "gpd1-3", "gpd1-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + + hs_i2c0_bus: hs-i2c0-bus { + samsung,pins = "gpd2-1", "gpd2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c1_bus: hs-i2c1-bus { + samsung,pins = "gpd2-3", "gpd2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c7_bus: hs-i2c7-bus { + samsung,pins = "gpd2-7", "gpd2-6"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c10_bus: hs-i2c10-bus { + samsung,pins = "gpg3-1", "gpg3-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c11_bus: hs-i2c11-bus { + samsung,pins = "gpg3-3", "gpg3-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi3_bus: spi3-bus { + samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi4_bus: spi4-bus { + samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpc1-1", "gpc0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_i2c: fimc-is-ch0_i2c { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_mclk: fimc-is-ch0_mclk { + samsung,pins = "gpd7-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_i2c: fimc-is-ch1-i2c { + samsung,pins = "gpc2-3", "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_mclk: fimc-is-ch1-mclk { + samsung,pins = "gpd7-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_i2c: fimc-is-ch2-i2c { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_mclk: fimc-is-ch2-mclk { + samsung,pins = "gpd7-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_touch { + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c5_bus: hs-i2c5-bus { + samsung,pins = "gpj1-1", "gpj1-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi new file mode 100644 index 0000000..2cc1375 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -0,0 +1,696 @@ +/* + * Samsung's Exynos5433 SoC device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5433 SoC device nodes are listed in this file. Exynos5433 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/exynos5433.h> + +/ { + compatible = "samsung,exynos5433"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_aud; + pinctrl2 = &pinctrl_cpif; + pinctrl3 = &pinctrl_ese; + pinctrl4 = &pinctrl_finger; + pinctrl5 = &pinctrl_fsys; + pinctrl6 = &pinctrl_imem; + pinctrl7 = &pinctrl_nfc; + pinctrl8 = &pinctrl_peric; + pinctrl9 = &pinctrl_touch; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + i2c8 = &hsi2c_8; + i2c9 = &hsi2c_9; + i2c10 = &hsi2c_10; + i2c11 = &hsi2c_11; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x102>; + }; + + cpu3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x103>; + }; + + cpu4: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu5: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu6: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu7: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x18000000>; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + xxti: xxti { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cmu_top: clock-controller@10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + }; + + cmu_cpif: clock-controller@10fc0000 { + compatible = "samsung,exynos5433-cmu-cpif"; + reg = <0x10fc0000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk"; + clocks = <&xxti>; + }; + + cmu_mif: clock-controller@105b0000 { + compatible = "samsung,exynos5433-cmu-mif"; + reg = <0x105b0000 0x100c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>; + }; + + cmu_peric: clock-controller@14c80000 { + compatible = "samsung,exynos5433-cmu-peric"; + reg = <0x14c80000 0x0b08>; + #clock-cells = <1>; + }; + + cmu_peris: clock-controller@0x10040000 { + compatible = "samsung,exynos5433-cmu-peris"; + reg = <0x10040000 0x0b20>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller@156e0000 { + compatible = "samsung,exynos5433-cmu-fsys"; + reg = <0x156e0000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_ufs_mphy", + "div_aclk_fsys_200", + "sclk_pcie_100_fsys", + "sclk_ufsunipro_fsys", + "sclk_mmc2_fsys", + "sclk_mmc1_fsys", + "sclk_mmc0_fsys", + "sclk_usbhost30_fsys", + "sclk_usbdrd30_fsys"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_UFS_MPHY>, + <&cmu_top CLK_DIV_ACLK_FSYS_200>, + <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, + <&cmu_top CLK_SCLK_MMC2_FSYS>, + <&cmu_top CLK_SCLK_MMC1_FSYS>, + <&cmu_top CLK_SCLK_MMC0_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + }; + + cmu_g2d: clock-controller@12460000 { + compatible = "samsung,exynos5433-cmu-g2d"; + reg = <0x12460000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_g2d_266", + "aclk_g2d_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_G2D_266>, + <&cmu_top CLK_ACLK_G2D_400>; + }; + + cmu_disp: clock-controller@13b90000 { + compatible = "samsung,exynos5433-cmu-disp"; + reg = <0x13b90000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_dsim1_disp", + "sclk_dsim0_disp", + "sclk_dsd_disp", + "sclk_decon_tv_eclk_disp", + "sclk_decon_vclk_disp", + "sclk_decon_eclk_disp", + "sclk_decon_tv_vclk_disp", + "aclk_disp_333"; + clocks = <&xxti>, + <&cmu_mif CLK_SCLK_DSIM1_DISP>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_mif CLK_SCLK_DSD_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, + <&cmu_mif CLK_ACLK_DISP_333>; + }; + + cmu_aud: clock-controller@114c0000 { + compatible = "samsung,exynos5433-cmu-aud"; + reg = <0x114c0000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus0: clock-controller@13600000 { + compatible = "samsung,exynos5433-cmu-bus0"; + reg = <0x13600000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus0_400"; + clocks = <&cmu_top CLK_ACLK_BUS0_400>; + }; + + cmu_bus1: clock-controller@14800000 { + compatible = "samsung,exynos5433-cmu-bus1"; + reg = <0x14800000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus1_400"; + clocks = <&cmu_top CLK_ACLK_BUS1_400>; + }; + + cmu_bus2: clock-controller@13400000 { + compatible = "samsung,exynos5433-cmu-bus2"; + reg = <0x13400000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_bus2_400"; + clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; + }; + + cmu_g3d: clock-controller@14aa0000 { + compatible = "samsung,exynos5433-cmu-g3d"; + reg = <0x14aa0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_g3d_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + }; + + cmu_gscl: clock-controller@13cf0000 { + compatible = "samsung,exynos5433-cmu-gscl"; + reg = <0x13cf0000 0x0b10>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_gscl_111", + "aclk_gscl_333"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; + }; + + cmu_apollo: clock-controller@11900000 { + compatible = "samsung,exynos5433-cmu-apollo"; + reg = <0x11900000 0x1088>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_apollo"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; + }; + + cmu_atlas: clock-controller@11800000 { + compatible = "samsung,exynos5433-cmu-atlas"; + reg = <0x11800000 0x1088>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_atlas"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; + }; + + cmu_mscl: clock-controller@105d0000 { + compatible = "samsung,exynos5433-cmu-mscl"; + reg = <0x105d0000 0x0b10>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_jpeg_mscl", + "aclk_mscl_400"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_JPEG_MSCL>, + <&cmu_top CLK_ACLK_MSCL_400>; + }; + + cmu_mfc: clock-controller@15280000 { + compatible = "samsung,exynos5433-cmu-mfc"; + reg = <0x15280000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_mfc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + }; + + cmu_hevc: clock-controller@14f80000 { + compatible = "samsung,exynos5433-cmu-hevc"; + reg = <0x14f80000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_hevc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + }; + + cmu_isp: clock-controller@146d0000 { + compatible = "samsung,exynos5433-cmu-isp"; + reg = <0x146d0000 0x0b0c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_isp_dis_400", + "aclk_isp_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_ISP_DIS_400>, + <&cmu_top CLK_ACLK_ISP_400>; + }; + + cmu_cam0: clock-controller@120d0000 { + compatible = "samsung,exynos5433-cmu-cam0"; + reg = <0x120d0000 0x0b0c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_cam0_333", + "aclk_cam0_400", + "aclk_cam0_552"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_CAM0_333>, + <&cmu_top CLK_ACLK_CAM0_400>, + <&cmu_top CLK_ACLK_CAM0_552>; + }; + + cmu_cam1: clock-controller@145d0000 { + compatible = "samsung,exynos5433-cmu-cam1"; + reg = <0x145d0000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_isp_uart_cam1", + "sclk_isp_spi1_cam1", + "sclk_isp_spi0_cam1", + "aclk_cam1_333", + "aclk_cam1_400", + "aclk_cam1_552"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_ISP_UART_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, + <&cmu_top CLK_ACLK_CAM1_333>, + <&cmu_top CLK_ACLK_CAM1_400>, + <&cmu_top CLK_ACLK_CAM1_552>; + }; + + mct@101c0000 { + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; + reg = <0x101c0000 0x800>; + interrupts = <0 102 0>, <0 103 0>, <0 104 0>, <0 105 0>, + <0 106 0>, <0 107 0>, <0 108 0>, <0 109 0>, + <0 110 0>, <0 111 0>, <0 112 0>, <0 113 0>; + clocks = <&xxti>, + <&cmu_peris CLK_PCLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + gic:interrupt-controller@11001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x11001000 0x1000>, + <0x11002000 0x2000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + serial_0: serial@14c10000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c10000 0x100>; + interrupts = <0 421 0>; + clocks = <&cmu_peric CLK_PCLK_UART0>, + <&cmu_peric CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + status = "disabled"; + }; + + serial_1: serial@14c20000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c20000 0x100>; + interrupts = <0 422 0>; + clocks = <&cmu_peric CLK_PCLK_UART1>, + <&cmu_peric CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + status = "disabled"; + }; + + serial_2: serial@14c30000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c30000 0x100>; + interrupts = <0 423 0>; + clocks = <&cmu_peric CLK_PCLK_UART2>, + <&cmu_peric CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + status = "disabled"; + }; + + pinctrl_alive: pinctrl@10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = <0 16 0>; + }; + }; + + pinctrl_aud: pinctrl@114b0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x114b0000 0x1000>; + interrupts = <0 68 0>; + }; + + pinctrl_cpif: pinctrl@10fe0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10fe0000 0x1000>; + interrupts = <0 179 0>; + }; + + pinctrl_ese: pinctrl@14ca0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14ca0000 0x1000>; + interrupts = <0 413 0>; + }; + + pinctrl_finger: pinctrl@14cb0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cb0000 0x1000>; + interrupts = <0 414 0>; + }; + + pinctrl_fsys: pinctrl@15690000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x15690000 0x1000>; + interrupts = <0 229 0>; + }; + + pinctrl_imem: pinctrl@11090000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x11090000 0x1000>; + interrupts = <0 325 0>; + }; + + pinctrl_nfc: pinctrl@14cd0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cd0000 0x1000>; + interrupts = <0 441 0>; + }; + + pinctrl_peric: pinctrl@14cc0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cc0000 0x1100>; + interrupts = <0 440 0>; + }; + + pinctrl_touch: pinctrl@14ce0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14ce0000 0x1100>; + interrupts = <0 442 0>; + }; + + hsi2c_0: hsi2c@14e40000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e40000 0x1000>; + interrupts = <0 428 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c0_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: hsi2c@14e50000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e50000 0x1000>; + interrupts = <0 429 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c1_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: hsi2c@14e60000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e60000 0x1000>; + interrupts = <0 430 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c2_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: hsi2c@14e70000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e70000 0x1000>; + interrupts = <0 431 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c3_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_4: hsi2c@14ec0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ec0000 0x1000>; + interrupts = <0 424 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c4_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C4>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: hsi2c@14ed0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ed0000 0x1000>; + interrupts = <0 425 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c5_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C5>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: hsi2c@14ee0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ee0000 0x1000>; + interrupts = <0 426 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c6_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C6>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: hsi2c@14ef0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ef0000 0x1000>; + interrupts = <0 427 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c7_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C7>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_8: hsi2c@14d90000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14d90000 0x1000>; + interrupts = <0 443 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c8_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C8>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_9: hsi2c@14da0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14da0000 0x1000>; + interrupts = <0 444 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c9_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C9>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_10: hsi2c@14de0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14de0000 0x1000>; + interrupts = <0 445 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c10_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C10>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_11: hsi2c@14df0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14df0000 0x1000>; + interrupts = <0 446 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c11_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C11>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff04>, + <1 14 0xff04>, + <1 11 0xff04>, + <1 10 0xff04>; + }; + }; +}; + +#include "exynos5433-pinctrl.dtsi" -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/8] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following dt node to support Exynos5433 SoC: 1. Octa core for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Support PSCI v0.1 2. clock controller node: - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. pinctrl node for GPIO: - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. HS (High-Speed) I2C device 5. Serial device 6. ARCH timer (arm,armv8-timer) 7. Interrupt controller (arm,gic-400) Cc: Kukjin Kim <kgene@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 698 +++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 696 ++++++++++++++++++++ 2 files changed, 1394 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi new file mode 100644 index 0000000..81fe925 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -0,0 +1,698 @@ +/* + * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_aud { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", + "gpz0-4", "gpz0-5", "gpz0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm0_bus: pcm0-bus { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_cpif { + gpv6: gpv6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_ese { + gpj2: gpj2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_finger { + gpd5: gpd5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c6_bus: hs-i2c6-bus { + samsung,pins = "gpd5-3", "gpd5-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + +}; + +&pinctrl_fsys { + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr4: gpr4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr0: gpr0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr1: gpr1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr2: gpr2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpr3: gpr3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + sd0_clk: sd0-clk { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpr0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpr0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_qrdy: sd0-qrdy { + samsung,pins = "gpr0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpr1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpr2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpr2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpr3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + pcie_bus: pcie_bus { + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpr4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpr4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpr4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk_output: sd2-clk-output { + samsung,pins = "gpr4-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd_output: sd2-cmd-output { + samsung,pins = "gpr4-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; +}; + +&pinctrl_imem { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_nfc { + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c4_bus: hs-i2c4-bus { + samsung,pins = "gpj0-1", "gpj0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + +}; + +&pinctrl_peric { + gpv7: gpv7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd4: gpd4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd8: gpd8 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd6: gpd6 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd7: gpd7 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c8_bus: hs-i2c8-bus { + samsung,pins = "gpb0-1", "gpb0-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c9_bus: hs-i2c9-bus { + samsung,pins = "gpb0-3", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", + "gpd4-3", "gpd4-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + spdif_bus: spdif-bus { + samsung,pins = "gpd4-3", "gpd4-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin0: fimc-is-spi-pin0 { + samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_spi_pin1: fimc-is-spi-pin1 { + samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_bus: uart0-bus { + samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c2_bus: hs-i2c2-bus { + samsung,pins = "gpd0-3", "gpd0-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + uart2_bus: uart2-bus { + samsung,pins = "gpd1-5", "gpd1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart1_bus: uart1-bus { + samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + hs_i2c3_bus: hs-i2c3-bus { + samsung,pins = "gpd1-3", "gpd1-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + + hs_i2c0_bus: hs-i2c0-bus { + samsung,pins = "gpd2-1", "gpd2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c1_bus: hs-i2c1-bus { + samsung,pins = "gpd2-3", "gpd2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c7_bus: hs-i2c7-bus { + samsung,pins = "gpd2-7", "gpd2-6"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c10_bus: hs-i2c10-bus { + samsung,pins = "gpg3-1", "gpg3-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hs_i2c11_bus: hs-i2c11-bus { + samsung,pins = "gpg3-3", "gpg3-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi3_bus: spi3-bus { + samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi4_bus: spi4-bus { + samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpc1-1", "gpc0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_i2c: fimc-is-ch0_i2c { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch0_mclk: fimc-is-ch0_mclk { + samsung,pins = "gpd7-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_i2c: fimc-is-ch1-i2c { + samsung,pins = "gpc2-3", "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch1_mclk: fimc-is-ch1-mclk { + samsung,pins = "gpd7-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_i2c: fimc-is-ch2-i2c { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_ch2_mclk: fimc-is-ch2-mclk { + samsung,pins = "gpd7-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_touch { + gpj1: gpj1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c5_bus: hs-i2c5-bus { + samsung,pins = "gpj1-1", "gpj1-0"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi new file mode 100644 index 0000000..2cc1375 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -0,0 +1,696 @@ +/* + * Samsung's Exynos5433 SoC device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5433 SoC device nodes are listed in this file. Exynos5433 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/exynos5433.h> + +/ { + compatible = "samsung,exynos5433"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_aud; + pinctrl2 = &pinctrl_cpif; + pinctrl3 = &pinctrl_ese; + pinctrl4 = &pinctrl_finger; + pinctrl5 = &pinctrl_fsys; + pinctrl6 = &pinctrl_imem; + pinctrl7 = &pinctrl_nfc; + pinctrl8 = &pinctrl_peric; + pinctrl9 = &pinctrl_touch; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + i2c8 = &hsi2c_8; + i2c9 = &hsi2c_9; + i2c10 = &hsi2c_10; + i2c11 = &hsi2c_11; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu1: cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu2: cpu at 102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x102>; + }; + + cpu3: cpu at 103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x103>; + }; + + cpu4: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu5: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu6: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu7: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x18000000>; + + chipid at 10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + xxti: xxti { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cmu_top: clock-controller at 10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + }; + + cmu_cpif: clock-controller at 10fc0000 { + compatible = "samsung,exynos5433-cmu-cpif"; + reg = <0x10fc0000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk"; + clocks = <&xxti>; + }; + + cmu_mif: clock-controller at 105b0000 { + compatible = "samsung,exynos5433-cmu-mif"; + reg = <0x105b0000 0x100c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>; + }; + + cmu_peric: clock-controller at 14c80000 { + compatible = "samsung,exynos5433-cmu-peric"; + reg = <0x14c80000 0x0b08>; + #clock-cells = <1>; + }; + + cmu_peris: clock-controller at 0x10040000 { + compatible = "samsung,exynos5433-cmu-peris"; + reg = <0x10040000 0x0b20>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller at 156e0000 { + compatible = "samsung,exynos5433-cmu-fsys"; + reg = <0x156e0000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_ufs_mphy", + "div_aclk_fsys_200", + "sclk_pcie_100_fsys", + "sclk_ufsunipro_fsys", + "sclk_mmc2_fsys", + "sclk_mmc1_fsys", + "sclk_mmc0_fsys", + "sclk_usbhost30_fsys", + "sclk_usbdrd30_fsys"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_UFS_MPHY>, + <&cmu_top CLK_DIV_ACLK_FSYS_200>, + <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, + <&cmu_top CLK_SCLK_MMC2_FSYS>, + <&cmu_top CLK_SCLK_MMC1_FSYS>, + <&cmu_top CLK_SCLK_MMC0_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + }; + + cmu_g2d: clock-controller at 12460000 { + compatible = "samsung,exynos5433-cmu-g2d"; + reg = <0x12460000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_g2d_266", + "aclk_g2d_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_G2D_266>, + <&cmu_top CLK_ACLK_G2D_400>; + }; + + cmu_disp: clock-controller at 13b90000 { + compatible = "samsung,exynos5433-cmu-disp"; + reg = <0x13b90000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_dsim1_disp", + "sclk_dsim0_disp", + "sclk_dsd_disp", + "sclk_decon_tv_eclk_disp", + "sclk_decon_vclk_disp", + "sclk_decon_eclk_disp", + "sclk_decon_tv_vclk_disp", + "aclk_disp_333"; + clocks = <&xxti>, + <&cmu_mif CLK_SCLK_DSIM1_DISP>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_mif CLK_SCLK_DSD_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, + <&cmu_mif CLK_ACLK_DISP_333>; + }; + + cmu_aud: clock-controller at 114c0000 { + compatible = "samsung,exynos5433-cmu-aud"; + reg = <0x114c0000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus0: clock-controller at 13600000 { + compatible = "samsung,exynos5433-cmu-bus0"; + reg = <0x13600000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus0_400"; + clocks = <&cmu_top CLK_ACLK_BUS0_400>; + }; + + cmu_bus1: clock-controller at 14800000 { + compatible = "samsung,exynos5433-cmu-bus1"; + reg = <0x14800000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus1_400"; + clocks = <&cmu_top CLK_ACLK_BUS1_400>; + }; + + cmu_bus2: clock-controller at 13400000 { + compatible = "samsung,exynos5433-cmu-bus2"; + reg = <0x13400000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_bus2_400"; + clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; + }; + + cmu_g3d: clock-controller at 14aa0000 { + compatible = "samsung,exynos5433-cmu-g3d"; + reg = <0x14aa0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_g3d_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + }; + + cmu_gscl: clock-controller at 13cf0000 { + compatible = "samsung,exynos5433-cmu-gscl"; + reg = <0x13cf0000 0x0b10>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_gscl_111", + "aclk_gscl_333"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; + }; + + cmu_apollo: clock-controller at 11900000 { + compatible = "samsung,exynos5433-cmu-apollo"; + reg = <0x11900000 0x1088>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_apollo"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; + }; + + cmu_atlas: clock-controller at 11800000 { + compatible = "samsung,exynos5433-cmu-atlas"; + reg = <0x11800000 0x1088>; + #clock-cells = <1>; + + clock-names = "oscclk", "sclk_bus_pll_atlas"; + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; + }; + + cmu_mscl: clock-controller at 105d0000 { + compatible = "samsung,exynos5433-cmu-mscl"; + reg = <0x105d0000 0x0b10>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_jpeg_mscl", + "aclk_mscl_400"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_JPEG_MSCL>, + <&cmu_top CLK_ACLK_MSCL_400>; + }; + + cmu_mfc: clock-controller at 15280000 { + compatible = "samsung,exynos5433-cmu-mfc"; + reg = <0x15280000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_mfc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + }; + + cmu_hevc: clock-controller at 14f80000 { + compatible = "samsung,exynos5433-cmu-hevc"; + reg = <0x14f80000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_hevc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + }; + + cmu_isp: clock-controller at 146d0000 { + compatible = "samsung,exynos5433-cmu-isp"; + reg = <0x146d0000 0x0b0c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_isp_dis_400", + "aclk_isp_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_ISP_DIS_400>, + <&cmu_top CLK_ACLK_ISP_400>; + }; + + cmu_cam0: clock-controller at 120d0000 { + compatible = "samsung,exynos5433-cmu-cam0"; + reg = <0x120d0000 0x0b0c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_cam0_333", + "aclk_cam0_400", + "aclk_cam0_552"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_CAM0_333>, + <&cmu_top CLK_ACLK_CAM0_400>, + <&cmu_top CLK_ACLK_CAM0_552>; + }; + + cmu_cam1: clock-controller at 145d0000 { + compatible = "samsung,exynos5433-cmu-cam1"; + reg = <0x145d0000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_isp_uart_cam1", + "sclk_isp_spi1_cam1", + "sclk_isp_spi0_cam1", + "aclk_cam1_333", + "aclk_cam1_400", + "aclk_cam1_552"; + clocks = <&xxti>, + <&cmu_top CLK_SCLK_ISP_UART_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, + <&cmu_top CLK_ACLK_CAM1_333>, + <&cmu_top CLK_ACLK_CAM1_400>, + <&cmu_top CLK_ACLK_CAM1_552>; + }; + + mct at 101c0000 { + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; + reg = <0x101c0000 0x800>; + interrupts = <0 102 0>, <0 103 0>, <0 104 0>, <0 105 0>, + <0 106 0>, <0 107 0>, <0 108 0>, <0 109 0>, + <0 110 0>, <0 111 0>, <0 112 0>, <0 113 0>; + clocks = <&xxti>, + <&cmu_peris CLK_PCLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + gic:interrupt-controller at 11001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x11001000 0x1000>, + <0x11002000 0x2000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + serial_0: serial at 14c10000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c10000 0x100>; + interrupts = <0 421 0>; + clocks = <&cmu_peric CLK_PCLK_UART0>, + <&cmu_peric CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + status = "disabled"; + }; + + serial_1: serial at 14c20000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c20000 0x100>; + interrupts = <0 422 0>; + clocks = <&cmu_peric CLK_PCLK_UART1>, + <&cmu_peric CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + status = "disabled"; + }; + + serial_2: serial at 14c30000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14c30000 0x100>; + interrupts = <0 423 0>; + clocks = <&cmu_peric CLK_PCLK_UART2>, + <&cmu_peric CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + status = "disabled"; + }; + + pinctrl_alive: pinctrl at 10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = <0 16 0>; + }; + }; + + pinctrl_aud: pinctrl at 114b0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x114b0000 0x1000>; + interrupts = <0 68 0>; + }; + + pinctrl_cpif: pinctrl at 10fe0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10fe0000 0x1000>; + interrupts = <0 179 0>; + }; + + pinctrl_ese: pinctrl at 14ca0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14ca0000 0x1000>; + interrupts = <0 413 0>; + }; + + pinctrl_finger: pinctrl at 14cb0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cb0000 0x1000>; + interrupts = <0 414 0>; + }; + + pinctrl_fsys: pinctrl at 15690000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x15690000 0x1000>; + interrupts = <0 229 0>; + }; + + pinctrl_imem: pinctrl at 11090000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x11090000 0x1000>; + interrupts = <0 325 0>; + }; + + pinctrl_nfc: pinctrl at 14cd0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cd0000 0x1000>; + interrupts = <0 441 0>; + }; + + pinctrl_peric: pinctrl at 14cc0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14cc0000 0x1100>; + interrupts = <0 440 0>; + }; + + pinctrl_touch: pinctrl at 14ce0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x14ce0000 0x1100>; + interrupts = <0 442 0>; + }; + + hsi2c_0: hsi2c at 14e40000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e40000 0x1000>; + interrupts = <0 428 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c0_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: hsi2c at 14e50000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e50000 0x1000>; + interrupts = <0 429 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c1_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: hsi2c at 14e60000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e60000 0x1000>; + interrupts = <0 430 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c2_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: hsi2c at 14e70000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14e70000 0x1000>; + interrupts = <0 431 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c3_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_4: hsi2c at 14ec0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ec0000 0x1000>; + interrupts = <0 424 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c4_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C4>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: hsi2c at 14ed0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ed0000 0x1000>; + interrupts = <0 425 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c5_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C5>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: hsi2c at 14ee0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ee0000 0x1000>; + interrupts = <0 426 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c6_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C6>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: hsi2c at 14ef0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14ef0000 0x1000>; + interrupts = <0 427 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c7_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C7>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_8: hsi2c at 14d90000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14d90000 0x1000>; + interrupts = <0 443 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c8_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C8>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_9: hsi2c at 14da0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14da0000 0x1000>; + interrupts = <0 444 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c9_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C9>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_10: hsi2c at 14de0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14de0000 0x1000>; + interrupts = <0 445 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c10_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C10>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_11: hsi2c at 14df0000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x14df0000 0x1000>; + interrupts = <0 446 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c11_bus>; + clocks = <&cmu_peric CLK_PCLK_HSI2C11>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff04>, + <1 14 0xff04>, + <1 11 0xff04>, + <1 10 0xff04>; + }; + }; +}; + +#include "exynos5433-pinctrl.dtsi" -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
[parent not found: <1423724158-23632-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>]
* [PATCH v3 3/8] arm64: dts: exynos: Add MSHC dt node for Exynos5433 2015-02-12 6:55 ` Chanwoo Choi (?) @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: kgene-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8, marc.zyngier-5wv7dgnIgG8, arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w, catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8, sangbae90.lee-Sze3O3UU22JBDgjK7y7TUQ, inki.dae-Sze3O3UU22JBDgjK7y7TUQ, chanho61.park-Sze3O3UU22JBDgjK7y7TUQ, sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ, jh80.chung-Sze3O3UU22JBDgjK7y7TUQ, cw00.choi-Sze3O3UU22JBDgjK7y7TUQ, a.kesavan-Sze3O3UU22JBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r From: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433 SoC. MSHC is an interface between the system the SD/MMC card. Cc: Kukjin Kim <kgene-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> Cc: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> Cc: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> Cc: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Acked-by: Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 2cc1375..a151584 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -52,6 +52,9 @@ i2c9 = &hsi2c_9; i2c10 = &hsi2c_10; i2c11 = &hsi2c_11; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; }; cpus { @@ -683,6 +686,45 @@ status = "disabled"; }; + mshc_0: mshc@15540000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 225 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15540000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC0>, + <&cmu_fsys CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_1: mshc@15550000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 226 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15550000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC1>, + <&cmu_fsys CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_2: mshc@15560000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 227 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15560000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC2>, + <&cmu_fsys CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/8] arm64: dts: exynos: Add MSHC dt node for Exynos5433 @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel From: Jaehoon Chung <jh80.chung@samsung.com> This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433 SoC. MSHC is an interface between the system the SD/MMC card. Cc: Kukjin Kim <kgene@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 2cc1375..a151584 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -52,6 +52,9 @@ i2c9 = &hsi2c_9; i2c10 = &hsi2c_10; i2c11 = &hsi2c_11; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; }; cpus { @@ -683,6 +686,45 @@ status = "disabled"; }; + mshc_0: mshc@15540000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 225 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15540000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC0>, + <&cmu_fsys CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_1: mshc@15550000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 226 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15550000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC1>, + <&cmu_fsys CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_2: mshc@15560000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 227 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15560000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC2>, + <&cmu_fsys CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/8] arm64: dts: exynos: Add MSHC dt node for Exynos5433 @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel From: Jaehoon Chung <jh80.chung@samsung.com> This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433 SoC. MSHC is an interface between the system the SD/MMC card. Cc: Kukjin Kim <kgene@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 2cc1375..a151584 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -52,6 +52,9 @@ i2c9 = &hsi2c_9; i2c10 = &hsi2c_10; i2c11 = &hsi2c_11; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; }; cpus { @@ -683,6 +686,45 @@ status = "disabled"; }; + mshc_0: mshc at 15540000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 225 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15540000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC0>, + <&cmu_fsys CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_1: mshc at 15550000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 226 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15550000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC1>, + <&cmu_fsys CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mshc_2: mshc at 15560000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + interrupts = <0 227 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x15560000 0x2000>; + clocks = <&cmu_fsys CLK_ACLK_MMC2>, + <&cmu_fsys CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/8] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433 2015-02-12 6:55 ` Chanwoo Choi @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC. SPI transfers serial data by using various peripherals. SPI includes 8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used for SPI communication. Cc: Kukjin Kim <kgene@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 119 +++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index a151584..5477630 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -55,6 +55,11 @@ mshc0 = &mshc_0; mshc1 = &mshc_1; mshc2 = &mshc_2; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; }; cpus { @@ -430,6 +435,35 @@ interrupts = <1 9 0xf04>; }; + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma0: pdma@15610000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15610000 0x1000>; + interrupts = <0 228 0>; + clocks = <&cmu_fsys CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@15600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15600000 0x1000>; + interrupts = <0 246 0>; + clocks = <&cmu_fsys CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + serial_0: serial@14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>; @@ -530,6 +564,91 @@ interrupts = <0 442 0>; }; + spi_0: spi@14d20000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d20000 0x100>; + interrupts = <0 432 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI0>, + <&cmu_top CLK_SCLK_SPI0_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi@14d30000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d30000 0x100>; + interrupts = <0 433 0>; + dmas = <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI1>, + <&cmu_top CLK_SCLK_SPI1_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + spi_2: spi@14d40000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d40000 0x100>; + interrupts = <0 434 0>; + dmas = <&pdma0 13>, <&pdma0 12>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI2>, + <&cmu_top CLK_SCLK_SPI2_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + spi_3: spi@14d50000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d50000 0x100>; + interrupts = <0 447 0>; + dmas = <&pdma0 23>, <&pdma0 22>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI3>, + <&cmu_top CLK_SCLK_SPI3_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + status = "disabled"; + }; + + spi_4: spi@14d00000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d00000 0x100>; + interrupts = <0 412 0>; + dmas = <&pdma0 25>, <&pdma0 24>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI4>, + <&cmu_top CLK_SCLK_SPI4_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + status = "disabled"; + }; + hsi2c_0: hsi2c@14e40000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e40000 0x1000>; -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/8] arm64: dts: exynos: Add SPI/PDMA dt node for Exynos5433 @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC. SPI transfers serial data by using various peripherals. SPI includes 8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used for SPI communication. Cc: Kukjin Kim <kgene@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 119 +++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index a151584..5477630 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -55,6 +55,11 @@ mshc0 = &mshc_0; mshc1 = &mshc_1; mshc2 = &mshc_2; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; }; cpus { @@ -430,6 +435,35 @@ interrupts = <1 9 0xf04>; }; + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma0: pdma at 15610000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15610000 0x1000>; + interrupts = <0 228 0>; + clocks = <&cmu_fsys CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma at 15600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x15600000 0x1000>; + interrupts = <0 246 0>; + clocks = <&cmu_fsys CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + serial_0: serial at 14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>; @@ -530,6 +564,91 @@ interrupts = <0 442 0>; }; + spi_0: spi at 14d20000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d20000 0x100>; + interrupts = <0 432 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI0>, + <&cmu_top CLK_SCLK_SPI0_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi at 14d30000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d30000 0x100>; + interrupts = <0 433 0>; + dmas = <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI1>, + <&cmu_top CLK_SCLK_SPI1_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + spi_2: spi at 14d40000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d40000 0x100>; + interrupts = <0 434 0>; + dmas = <&pdma0 13>, <&pdma0 12>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI2>, + <&cmu_top CLK_SCLK_SPI2_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + spi_3: spi at 14d50000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d50000 0x100>; + interrupts = <0 447 0>; + dmas = <&pdma0 23>, <&pdma0 22>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI3>, + <&cmu_top CLK_SCLK_SPI3_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + status = "disabled"; + }; + + spi_4: spi at 14d00000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d00000 0x100>; + interrupts = <0 412 0>; + dmas = <&pdma0 25>, <&pdma0 24>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI4>, + <&cmu_top CLK_SCLK_SPI4_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + status = "disabled"; + }; + hsi2c_0: hsi2c at 14e40000 { compatible = "samsung,exynos7-hsi2c"; reg = <0x14e40000 0x1000>; -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 5/8] arm64: dts: exynos: Add PMU dt node for Exynos5433 2015-02-12 6:55 ` Chanwoo Choi @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel, Inha Song This patch adds PMU (Power Management Unit) dt node for Exynos5433 SoC and set the source clock for CLKOUT register as xxti . Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [ideal.song: Add the setting of CLKOUT register] Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 + arch/arm64/boot/dts/exynos/exynos5433.dtsi | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt index 67b2113..a87fc43 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt @@ -10,6 +10,7 @@ Properties: - "samsung,exynos5260-pmu" - for Exynos5260 SoC. - "samsung,exynos5410-pmu" - for Exynos5410 SoC, - "samsung,exynos5420-pmu" - for Exynos5420 SoC. + - "samsung,exynos5433-pmu" - for Exynos5433 SoC. - "samsung,exynos7-pmu" - for Exynos7 SoC. second value must be always "syscon". diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 5477630..0168786 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -844,6 +844,14 @@ status = "disabled"; }; + pmu_system_controller: system-controller@105c0000 { + compatible = "samsung,exynos5433-pmu", "syscon"; + reg = <0x105c0000 0x5008>; + #clock-cells = <1>; + clock-names = "clkout16"; + clocks = <&xxti>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 5/8] arm64: dts: exynos: Add PMU dt node for Exynos5433 @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel This patch adds PMU (Power Management Unit) dt node for Exynos5433 SoC and set the source clock for CLKOUT register as xxti . Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [ideal.song: Add the setting of CLKOUT register] Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- Documentation/devicetree/bindings/arm/samsung/pmu.txt | 1 + arch/arm64/boot/dts/exynos/exynos5433.dtsi | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt index 67b2113..a87fc43 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt @@ -10,6 +10,7 @@ Properties: - "samsung,exynos5260-pmu" - for Exynos5260 SoC. - "samsung,exynos5410-pmu" - for Exynos5410 SoC, - "samsung,exynos5420-pmu" - for Exynos5420 SoC. + - "samsung,exynos5433-pmu" - for Exynos5433 SoC. - "samsung,exynos7-pmu" - for Exynos7 SoC. second value must be always "syscon". diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 5477630..0168786 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -844,6 +844,14 @@ status = "disabled"; }; + pmu_system_controller: system-controller at 105c0000 { + compatible = "samsung,exynos5433-pmu", "syscon"; + reg = <0x105c0000 0x5008>; + #clock-cells = <1>; + clock-names = "clkout16"; + clocks = <&xxti>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 6/8] arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC 2015-02-12 6:55 ` Chanwoo Choi (?) @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: mark.rutland, jh80.chung, arnd, cw00.choi, marc.zyngier, catalin.marinas, will.deacon, a.kesavan, inki.dae, sw0312.kim, devicetree, kgene, sangbae90.lee, olof, chanho61.park, linux-arm-kernel This patch adds RTC (Real Time Clock) dt node for Exynos5433 SoC and adds ADC dt node for Exynos5433 SoC. The c1b501564c98a94b4(iio: adc: exynos_adc: Add support for exynos7) commit supports the ADC for Exynos7. Exynos5433's ADC IP is the same with Exynos7's ADC IP. Exynos5433 has a little different from ADCv2 on ADC_CON2 register. Exynos5433 don't contain OSEL/ESEL /HIGHF of ADC_CON2. Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0168786..8e9ca8d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -852,6 +852,24 @@ clocks = <&xxti>; }; + rtc: rtc@10590000 { + compatible = "samsung,exynos3250-rtc"; + reg = <0x10590000 0x100>; + interrupts = <0 385 0>, <0 386 0>; + status = "disabled"; + }; + + adc: adc@14d10000 { + compatible = "samsung,exynos7-adc"; + reg = <0x14d10000 0x100>; + interrupts = <0 438 0>; + clock-names = "adc"; + clocks = <&cmu_peric CLK_PCLK_ADCIF>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 6/8] arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel This patch adds RTC (Real Time Clock) dt node for Exynos5433 SoC and adds ADC dt node for Exynos5433 SoC. The c1b501564c98a94b4(iio: adc: exynos_adc: Add support for exynos7) commit supports the ADC for Exynos7. Exynos5433's ADC IP is the same with Exynos7's ADC IP. Exynos5433 has a little different from ADCv2 on ADC_CON2 register. Exynos5433 don't contain OSEL/ESEL /HIGHF of ADC_CON2. Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0168786..8e9ca8d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -852,6 +852,24 @@ clocks = <&xxti>; }; + rtc: rtc@10590000 { + compatible = "samsung,exynos3250-rtc"; + reg = <0x10590000 0x100>; + interrupts = <0 385 0>, <0 386 0>; + status = "disabled"; + }; + + adc: adc@14d10000 { + compatible = "samsung,exynos7-adc"; + reg = <0x14d10000 0x100>; + interrupts = <0 438 0>; + clock-names = "adc"; + clocks = <&cmu_peric CLK_PCLK_ADCIF>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 6/8] arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel This patch adds RTC (Real Time Clock) dt node for Exynos5433 SoC and adds ADC dt node for Exynos5433 SoC. The c1b501564c98a94b4(iio: adc: exynos_adc: Add support for exynos7) commit supports the ADC for Exynos7. Exynos5433's ADC IP is the same with Exynos7's ADC IP. Exynos5433 has a little different from ADCv2 on ADC_CON2 register. Exynos5433 don't contain OSEL/ESEL /HIGHF of ADC_CON2. Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0168786..8e9ca8d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -852,6 +852,24 @@ clocks = <&xxti>; }; + rtc: rtc at 10590000 { + compatible = "samsung,exynos3250-rtc"; + reg = <0x10590000 0x100>; + interrupts = <0 385 0>, <0 386 0>; + status = "disabled"; + }; + + adc: adc at 14d10000 { + compatible = "samsung,exynos7-adc"; + reg = <0x14d10000 0x100>; + interrupts = <0 438 0>; + clock-names = "adc"; + clocks = <&cmu_peric CLK_PCLK_ADCIF>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff04>, -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 7/8] arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC 2015-02-12 6:55 ` Chanwoo Choi @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel, Inha Song From: Inha Song <ideal.song@samsung.com> This patch adds ADMA (Advanced DMA) device tree node for Exynos5433 SoC. In Exynos5433 SoC, ADMA is used for I2S audio interface. Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8e9ca8d..7bf4dcf 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -462,6 +462,17 @@ #dma-channels = <8>; #dma-requests = <32>; }; + + adma: adma@11420000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11420000 0x1000>; + interrupts = <0 73 0>; + clocks = <&cmu_aud CLK_ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; }; serial_0: serial@14c10000 { -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 7/8] arm64: dts: exynos: Add ADMA dt node for Exynos5433 SoC @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel From: Inha Song <ideal.song@samsung.com> This patch adds ADMA (Advanced DMA) device tree node for Exynos5433 SoC. In Exynos5433 SoC, ADMA is used for I2S audio interface. Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8e9ca8d..7bf4dcf 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -462,6 +462,17 @@ #dma-channels = <8>; #dma-requests = <32>; }; + + adma: adma at 11420000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11420000 0x1000>; + interrupts = <0 73 0>; + clocks = <&cmu_aud CLK_ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; }; serial_0: serial at 14c10000 { -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 8/8] arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC 2015-02-12 6:55 ` Chanwoo Choi @ 2015-02-12 6:55 ` Chanwoo Choi -1 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-samsung-soc, linux-kernel Cc: kgene, mark.rutland, marc.zyngier, arnd, olof, catalin.marinas, will.deacon, sangbae90.lee, inki.dae, chanho61.park, sw0312.kim, jh80.chung, cw00.choi, a.kesavan, devicetree, linux-arm-kernel, Inha Song From: Inha Song <ideal.song@samsung.com> This patch adds I2S device tree node for Exynos5433 SoC. In Exynos5433 SoC, I2S0 is used for audio interface. Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7bf4dcf..807ad8e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -511,6 +511,23 @@ status = "disabled"; }; + i2s0: i2s0@11440000 { + compatible = "samsung,exynos7-i2s"; + reg = <0x11440000 0x100>; + dmas = <&adma 0 &adma 2>; + dma-names = "tx", "rx"; + interrupts = <0 70 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, + <&cmu_aud CLK_SCLK_AUD_I2S>, + <&cmu_aud CLK_SCLK_I2S_BCLK>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; + }; + pinctrl_alive: pinctrl@10580000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x10580000 0x1000>; -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 8/8] arm64: dts: exynos: Add I2S dt node for Exynos5433 SoC @ 2015-02-12 6:55 ` Chanwoo Choi 0 siblings, 0 replies; 25+ messages in thread From: Chanwoo Choi @ 2015-02-12 6:55 UTC (permalink / raw) To: linux-arm-kernel From: Inha Song <ideal.song@samsung.com> This patch adds I2S device tree node for Exynos5433 SoC. In Exynos5433 SoC, I2S0 is used for audio interface. Cc: Kukjin Kim <kgene@kernel.org> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7bf4dcf..807ad8e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -511,6 +511,23 @@ status = "disabled"; }; + i2s0: i2s0 at 11440000 { + compatible = "samsung,exynos7-i2s"; + reg = <0x11440000 0x100>; + dmas = <&adma 0 &adma 2>; + dma-names = "tx", "rx"; + interrupts = <0 70 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, + <&cmu_aud CLK_SCLK_AUD_I2S>, + <&cmu_aud CLK_SCLK_I2S_BCLK>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; + }; + pinctrl_alive: pinctrl at 10580000 { compatible = "samsung,exynos5433-pinctrl"; reg = <0x10580000 0x1000>; -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 25+ messages in thread
end of thread, other threads:[~2015-02-12 11:03 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
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2015-02-12 6:55 [PATCH v3 0/8] arm64: Add the support for new Exynos5433 SoC Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` [PATCH v3 1/8] arm64: exynos5433: Enable ARMv8 based Exynos5433 (SoC) support Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
[not found] ` <1423724158-23632-2-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-02-12 11:02 ` Catalin Marinas
2015-02-12 11:02 ` Catalin Marinas
2015-02-12 11:02 ` Catalin Marinas
2015-02-12 11:03 ` Chanwoo Choi
2015-02-12 11:03 ` Chanwoo Choi
2015-02-12 6:55 ` [PATCH v3 2/8] arm64: dts: exynos: Add dts files for 64-bit Exynos5433 SoC Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
[not found] ` <1423724158-23632-1-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
2015-02-12 6:55 ` [PATCH v3 3/8] arm64: dts: exynos: Add MSHC dt node for Exynos5433 Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` [PATCH v3 4/8] arm64: dts: exynos: Add SPI/PDMA " Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` [PATCH v3 5/8] arm64: dts: exynos: Add PMU " Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` [PATCH v3 6/8] arm64: dts: exynos: Add RTC and ADC dt node for Exynos5433 SoC Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` [PATCH v3 7/8] arm64: dts: exynos: Add ADMA " Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
2015-02-12 6:55 ` [PATCH v3 8/8] arm64: dts: exynos: Add I2S " Chanwoo Choi
2015-02-12 6:55 ` Chanwoo Choi
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