From: Paolo Bonzini <pbonzini@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>, Alexander Graf <agraf@suse.de>
Cc: mttcg@greensocs.com, Mark Burton <mark.burton@greensocs.com>,
qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] Help on TLB Flush
Date: Fri, 13 Feb 2015 10:34:47 +0100 [thread overview]
Message-ID: <54DDC537.5070003@redhat.com> (raw)
In-Reply-To: <CAFEAcA-s_14NkUsX7=6JLCCk4Z_hoQfNDqPdPQ2aTKCGQ-wwSA@mail.gmail.com>
On 12/02/2015 22:57, Peter Maydell wrote:
> The only
> requirement is that if the CPU that did the TLB maintenance
> op executes a DMB (barrier) then the TLB op must finish
> before the barrier completes execution. So you could split
> the "kick off TLB invalidate" and "make sure all CPUs
> are done" phases if you wanted. [cf v8 ARM ARM rev A.e
> section D4.7.2 and in particular the subsection on
> "ordering and completion".]
You can just make DMB start a new translation block. Then when the TLB
flush helpers call cpu_exit() or cpu_interrupt() the flush request is
serviced.
Paolo
next prev parent reply other threads:[~2015-02-13 9:35 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-12 14:35 [Qemu-devel] Help on TLB Flush Mark Burton
2015-02-12 14:45 ` Alexander Graf
2015-02-12 14:58 ` Peter Maydell
2015-02-12 15:38 ` Alexander Graf
2015-02-12 16:02 ` Mark Burton
2015-02-12 22:10 ` Lluís Vilanova
2015-02-13 7:16 ` Mark Burton
2015-02-13 7:24 ` Peter Maydell
2015-02-13 7:37 ` Mark Burton
2015-02-13 13:30 ` Lluís Vilanova
2015-02-13 13:32 ` Mark Burton
2015-02-12 22:02 ` Peter Maydell
2015-02-12 15:01 ` Peter Maydell
2015-02-12 15:08 ` Mark Burton
2015-02-12 15:19 ` Alexander Graf
2015-02-12 21:57 ` Peter Maydell
2015-02-13 9:34 ` Paolo Bonzini [this message]
2015-02-13 9:37 ` Mark Burton
2015-02-13 9:49 ` Paolo Bonzini
2015-02-12 15:31 ` Dr. David Alan Gilbert
2015-02-12 18:44 ` Mark Burton
2015-02-12 15:11 ` Mark Burton
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