From: Alexander Graf <agraf@suse.de>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Laszlo Ersek <lersek@redhat.com>,
Christoffer Dall <christoffer.dall@linaro.org>,
Marc Zyngier <marc.zyngier@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Peter Maydell <peter.maydell@linaro.org>,
KVM devel mailing list <kvm@vger.kernel.org>,
"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings
Date: Thu, 19 Feb 2015 16:27:17 +0100 [thread overview]
Message-ID: <54E600D5.4070803@suse.de> (raw)
In-Reply-To: <CAKv+Gu9zciD-KuRXbQhLJBgW6i4jk0-=hG6UrBWr6-g-uZkO1A@mail.gmail.com>
On 19.02.15 15:56, Ard Biesheuvel wrote:
> On 19 February 2015 at 14:50, Alexander Graf <agraf@suse.de> wrote:
>>
>>
>> On 19.02.15 11:54, Ard Biesheuvel wrote:
>>> This is a 0th order approximation of how we could potentially force the guest
>>> to avoid uncached mappings, at least from the moment the MMU is on. (Before
>>> that, all of memory is implicitly classified as Device-nGnRnE)
>>>
>>> The idea (patch #2) is to trap writes to MAIR_EL1, and replace uncached mappings
>>> with cached ones. This way, there is no need to mangle any guest page tables.
>>
>> Would you mind to give a brief explanation on what this does? What
>> happens to actually assigned devices that need to be mapped as uncached?
>> What happens to DMA from such devices when the guest assumes that it's
>> accessing RAM uncached and then triggers DMA?
>>
>
> On ARM, stage 2 mappings that are more strict will supersede stage 1
> mappings, so the idea is to use cached mappings exclusively for stage
> 1 so that the host is fully in control of the actual memory attributes
> by setting the attributes at stage 2. This also makes sense because
> the host will ultimately know better whether some range that the guest
> thinks is a device is actually a device or just emulated (no stage 2
> mapping), backed by host memory (such as the NOR flash read case) or
> backed by a passthrough device.
Ok, so that means if the guest maps RAM as uncached, it will actually
end up as cached memory. Now if the guest triggers a DMA request to a
passed through device to that RAM, it will conflict with the cache.
I don't know whether it's a big deal, but it's the scenario that came up
with the approach above before when I talked to people about it.
Alex
WARNING: multiple messages have this Message-ID (diff)
From: agraf@suse.de (Alexander Graf)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings
Date: Thu, 19 Feb 2015 16:27:17 +0100 [thread overview]
Message-ID: <54E600D5.4070803@suse.de> (raw)
In-Reply-To: <CAKv+Gu9zciD-KuRXbQhLJBgW6i4jk0-=hG6UrBWr6-g-uZkO1A@mail.gmail.com>
On 19.02.15 15:56, Ard Biesheuvel wrote:
> On 19 February 2015 at 14:50, Alexander Graf <agraf@suse.de> wrote:
>>
>>
>> On 19.02.15 11:54, Ard Biesheuvel wrote:
>>> This is a 0th order approximation of how we could potentially force the guest
>>> to avoid uncached mappings, at least from the moment the MMU is on. (Before
>>> that, all of memory is implicitly classified as Device-nGnRnE)
>>>
>>> The idea (patch #2) is to trap writes to MAIR_EL1, and replace uncached mappings
>>> with cached ones. This way, there is no need to mangle any guest page tables.
>>
>> Would you mind to give a brief explanation on what this does? What
>> happens to actually assigned devices that need to be mapped as uncached?
>> What happens to DMA from such devices when the guest assumes that it's
>> accessing RAM uncached and then triggers DMA?
>>
>
> On ARM, stage 2 mappings that are more strict will supersede stage 1
> mappings, so the idea is to use cached mappings exclusively for stage
> 1 so that the host is fully in control of the actual memory attributes
> by setting the attributes at stage 2. This also makes sense because
> the host will ultimately know better whether some range that the guest
> thinks is a device is actually a device or just emulated (no stage 2
> mapping), backed by host memory (such as the NOR flash read case) or
> backed by a passthrough device.
Ok, so that means if the guest maps RAM as uncached, it will actually
end up as cached memory. Now if the guest triggers a DMA request to a
passed through device to that RAM, it will conflict with the cache.
I don't know whether it's a big deal, but it's the scenario that came up
with the approach above before when I talked to people about it.
Alex
next prev parent reply other threads:[~2015-02-19 15:27 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-19 10:54 [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings Ard Biesheuvel
2015-02-19 10:54 ` Ard Biesheuvel
2015-02-19 10:54 ` [RFC/RFT PATCH 1/3] arm64: KVM: handle some sysreg writes in EL2 Ard Biesheuvel
2015-02-19 10:54 ` Ard Biesheuvel
2015-03-03 17:59 ` Mario Smarduch
2015-03-03 17:59 ` Mario Smarduch
2015-02-19 10:54 ` [RFC/RFT PATCH 2/3] arm64: KVM: mangle MAIR register to prevent uncached guest mappings Ard Biesheuvel
2015-02-19 10:54 ` Ard Biesheuvel
2015-02-19 10:54 ` [RFC/RFT PATCH 3/3] arm64: KVM: keep trapping of VM sysreg writes enabled Ard Biesheuvel
2015-02-19 10:54 ` Ard Biesheuvel
2015-02-19 13:40 ` Marc Zyngier
2015-02-19 13:40 ` Marc Zyngier
2015-02-19 13:44 ` Ard Biesheuvel
2015-02-19 13:44 ` Ard Biesheuvel
2015-02-19 15:19 ` Marc Zyngier
2015-02-19 15:19 ` Marc Zyngier
2015-02-19 15:22 ` Ard Biesheuvel
2015-02-19 15:22 ` Ard Biesheuvel
2015-02-19 14:50 ` [RFC/RFT PATCH 0/3] arm64: KVM: work around incoherency with uncached guest mappings Alexander Graf
2015-02-19 14:50 ` Alexander Graf
2015-02-19 14:56 ` Ard Biesheuvel
2015-02-19 14:56 ` Ard Biesheuvel
2015-02-19 15:27 ` Alexander Graf [this message]
2015-02-19 15:27 ` Alexander Graf
2015-02-19 15:31 ` Ard Biesheuvel
2015-02-19 15:31 ` Ard Biesheuvel
2015-02-19 16:57 ` Andrew Jones
2015-02-19 16:57 ` Andrew Jones
2015-02-19 17:19 ` Ard Biesheuvel
2015-02-19 17:19 ` Ard Biesheuvel
2015-02-19 17:55 ` Andrew Jones
2015-02-19 17:55 ` Andrew Jones
2015-02-19 17:57 ` Paolo Bonzini
2015-02-19 17:57 ` Paolo Bonzini
2015-02-20 14:29 ` Andrew Jones
2015-02-20 14:29 ` Andrew Jones
2015-02-20 14:37 ` Ard Biesheuvel
2015-02-20 14:37 ` Ard Biesheuvel
2015-02-20 15:36 ` Andrew Jones
2015-02-20 15:36 ` Andrew Jones
2015-02-24 14:55 ` Andrew Jones
2015-02-24 14:55 ` Andrew Jones
2015-02-24 17:47 ` Ard Biesheuvel
2015-02-24 17:47 ` Ard Biesheuvel
2015-02-24 19:12 ` Andrew Jones
2015-02-24 19:12 ` Andrew Jones
2015-03-02 16:31 ` Christoffer Dall
2015-03-02 16:31 ` Christoffer Dall
2015-03-02 16:47 ` Paolo Bonzini
2015-03-02 16:47 ` Paolo Bonzini
2015-03-02 16:55 ` Laszlo Ersek
2015-03-02 16:55 ` Laszlo Ersek
2015-03-02 17:05 ` Andrew Jones
2015-03-02 17:05 ` Andrew Jones
2015-03-02 16:48 ` Andrew Jones
2015-03-02 16:48 ` Andrew Jones
2015-03-03 2:20 ` Mario Smarduch
2015-03-03 2:20 ` Mario Smarduch
2015-03-04 11:35 ` Catalin Marinas
2015-03-04 11:35 ` Catalin Marinas
2015-03-04 11:50 ` Ard Biesheuvel
2015-03-04 11:50 ` Ard Biesheuvel
2015-03-04 12:29 ` Catalin Marinas
2015-03-04 12:29 ` Catalin Marinas
2015-03-04 12:43 ` Ard Biesheuvel
2015-03-04 12:43 ` Ard Biesheuvel
2015-03-04 14:12 ` Andrew Jones
2015-03-04 14:12 ` Andrew Jones
2015-03-04 14:29 ` Catalin Marinas
2015-03-04 14:29 ` Catalin Marinas
2015-03-04 14:34 ` Peter Maydell
2015-03-04 14:34 ` Peter Maydell
2015-03-04 17:03 ` Paolo Bonzini
2015-03-04 17:03 ` Paolo Bonzini
2015-03-04 17:28 ` Catalin Marinas
2015-03-04 17:28 ` Catalin Marinas
2015-03-05 10:12 ` Paolo Bonzini
2015-03-05 10:12 ` Paolo Bonzini
2015-03-05 11:04 ` Catalin Marinas
2015-03-05 11:04 ` Catalin Marinas
2015-03-05 11:52 ` Peter Maydell
2015-03-05 11:52 ` Peter Maydell
2015-03-05 12:03 ` Catalin Marinas
2015-03-05 12:03 ` Catalin Marinas
2015-03-05 12:26 ` Paolo Bonzini
2015-03-05 12:26 ` Paolo Bonzini
2015-03-05 14:58 ` Catalin Marinas
2015-03-05 14:58 ` Catalin Marinas
2015-03-05 17:43 ` Paolo Bonzini
2015-03-05 17:43 ` Paolo Bonzini
2015-03-06 21:08 ` Mario Smarduch
2015-03-06 21:08 ` Mario Smarduch
2015-03-09 14:26 ` Andrew Jones
2015-03-09 14:26 ` Andrew Jones
2015-03-09 15:33 ` Mario Smarduch
2015-03-09 15:33 ` Mario Smarduch
2015-03-05 19:13 ` Ard Biesheuvel
2015-03-05 19:13 ` Ard Biesheuvel
2015-03-06 20:33 ` Mario Smarduch
2015-03-06 20:33 ` Mario Smarduch
2015-02-19 18:44 ` Ard Biesheuvel
2015-02-19 18:44 ` Ard Biesheuvel
2015-03-03 17:34 ` Alexander Graf
2015-03-03 17:34 ` Alexander Graf
2015-03-03 18:13 ` Laszlo Ersek
2015-03-03 18:13 ` Laszlo Ersek
2015-03-03 20:58 ` Andrew Jones
2015-03-03 20:58 ` Andrew Jones
2015-03-03 18:32 ` Catalin Marinas
2015-03-03 18:32 ` Catalin Marinas
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