Re: [Qemu-devel] [PATCH] target-tilegx: Finish decoding the first TB block.

[Chen Gang S <gang.chen@sunrus.com.cn>]

I guess, y2 does not need tcg temporary variables either, since it is
only for ld/st operation (all memory operations must be only processed
by y2 or x1).

At present, I can generate the tcg code for _start TB block, and can
execute to 2nd TB block __libc_start_main (although I don't know whether
the execution is correct or not).

But I guess, I have to fix current issue firstly, before continue.

Thanks.

On 2/21/15 23:31, Chen Gang S wrote:
> 
> Oh, we can not only assume y1 and x1 is the last execution in a bundle,
> e.g. in __libc_start_main:
> 
>    11330:       c6f106c685928d8a        { addi r10, sp, 40 ; addi r13, sp, 32 ; st r25, r30 }
>    11338:       2862014010000fca        { moveli r10, 0 ; st r10, r0 }
> 
> In this case, r10 will be over written. I have to use tcg temporary
> variables for it in each bundle:
> 
>  - We can still use the original pipes order: "y0, y2, y1" and "x0, x1".
> 
>  - y0, y2, and x0 need to use tcg temporary variables, but y1 and x1 can
>    still use real variables.
> 
>  - y1 and x1 need to flush the temporary variables, they also need to
>    consider about jump cases for tcg code (flush tcg temporary variables
>    after comparing and before jump).
> 
> 
> Welcome any ideas, suggestions or completions.
> 
> Thanks.
> 
> On 2/21/15 15:16, Chen Gang S wrote:
>> On 2/21/15 11:05, Chen Gang S wrote:
>>> At present finish decoding the first TB block: _start. Always let y1 and
>>> x1 pipe at the last which may content jump instructions.
>>>
>>> The related disassembly code is below which is the same as the objdump:
>>>
>>>   y0: 00000000500bfdb4  move r52, r54
>>>   y2: 0208000007600000  ld r1, r54
>>>   y1: 1c06400000000000  fnop
>>>   x0: 0000000051483000  fnop
>>>   x1: 180f86c600000000  addi r12, r54, -16
>>>   x0: 00000000403f8336  andi r54, r12, -8
>>>   x1: 286af00680000000  lnk r13
>>>   y0: 00000000500bf005  move r5, r0
>>>   y2: 03f8000007600000  st r54, r63
>>>   y1: 040046c600000000  addi r12, r54, 8
>>>   y0: 00000000500bfff7  move r55, r63
>>>   y2: 03f8000004c00000  st r12, r63
>>>   y1: 0400468100000000  addi r2, r52, 8
>>>   x0: 0000000040110d86  addi r6, r54, 16
>>>   x1: 07ffffe000000000  moveli r0, -1
>>>   x0: 000000007ffff000  shl16insli r0, r0, -1
>>>   x1: 000007e180000000  moveli r3, 0
>>>   x0: 000000007ffa8000  shl16insli r0, r0, -88
>>>   x1: 3800006180000000  shl16insli r3, r3, 0
>>>   x0: 00000000500cd000  and r0, r0, r13
>>>   x1: 3877406180000000  shl16insli r3, r3, 3816
>>>   x0: 0000000010000fcc  moveli r12, 0
>>>   x1: 2806686180000000  add r3, r3, r13
>>>   x0: 000000007000030c  shl16insli r12, r12, 0
>>>   x1: 000007e200000000  moveli r4, 0
>>>   x0: 000000007039030c  shl16insli r12, r12, 912
>>>   x1: 3800008200000000  shl16insli r4, r4, 0
>>>   x0: 00000000500cd30c  and r12, r12, r13
>>>   x1: 3881808200000000  shl16insli r4, r4, 4144
>>>   x0: 00000000500cd104  and r4, r4, r13
>>>   x1: 286a718000000000  jr r12
>>>
>>
>> Oh, sorry, it has no 'and' operation, it should be 'add' (3 places need
>> be modified). It is a printing typo issue.
>>
>> [...] 
>>> +    case 0x0000000050000000ULL:
>>> +        switch (TILEGX_CODE_X0_18(bundle)) {
>>> +        /* add Dest, SrcA, SrcB */
>>> +        case 0x00000000000c0000ULL:
>>> +            rdest = (unsigned char)(bundle & TILEGX_DATA_REGISTER);
>>> +            rsrc = (unsigned char)((bundle >> 6) & TILEGX_DATA_REGISTER);
>>> +            rsrcb = (unsigned char)((bundle >> 12) & TILEGX_DATA_REGISTER);
>>> +            qemu_log("and r%d, r%d, r%d", rdest, rsrc, rsrcb);
>>
>> It should be print "add", not "and".
>>
>> Thanks.
>>
> 

-- 
Chen Gang

Open, share, and attitude like air, water, and life which God blessed