From: Alexander Graf <agraf@suse.de>
To: Claudio Fontana <claudio.fontana@huawei.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] QEMU pci mach-virt: setting PCI_INTERRUPT_LINE?
Date: Wed, 25 Feb 2015 13:08:54 +0100 [thread overview]
Message-ID: <54EDBB56.10205@suse.de> (raw)
In-Reply-To: <54EDBB0A.7020009@huawei.com>
On 25.02.15 13:07, Claudio Fontana wrote:
>
>
> On 24.02.2015 15:34, Claudio Fontana wrote:
>> Hello,
>>
>> I am trying to set the pci interrupt line field in the configuration space
>> (offset 0x3c), since it is initialized as zero.
>>
>> I would like to set it to the right value as read from the device tree,
>> in order for other existing software which relies on it to be able to work unmodified..
>>
>> but it does not seem to work (I seem to read back zero even after setting the PCI_INTERRUPT_LINE field).
>>
>> I am also reading the interrupt pin, but that one instead seems to work out of the box..
>>
>> Thank you for any suggestion,
>>
>> Claudio
>
> By the way, I am currently just avoiding to rely on PCI_INTERRUPT_LINE for AArch64,
> but shouldn't the register be programmable?
As far as I understand the register should really just be a scratch r/w
register, yeah. Are you sure you're writing in byte granularity?
Alex
next prev parent reply other threads:[~2015-02-25 12:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-24 14:34 [Qemu-devel] QEMU pci mach-virt: setting PCI_INTERRUPT_LINE? Claudio Fontana
2015-02-25 12:07 ` Claudio Fontana
2015-02-25 12:08 ` Alexander Graf [this message]
2015-02-25 12:16 ` Claudio Fontana
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