All of lore.kernel.org
 help / color / mirror / Atom feed
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
To: Brian Norris <computersforpeace@gmail.com>,
	Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
	Jason Cooper <jason@lakedaemon.net>,
	Tawfik Bayouk <tawfik@marvell.com>,
	Thomas Petazzoni <thomas@free-electrons.com>,
	Seif Mazareeb <seif@marvell.com>,
	linux-kernel@vger.kernel.org, stable@vger.kernel.org,
	Sudhakar Gundubogula <sudhakar@marvell.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Boris Brezillon <boris@free-electrons.com>,
	linux-mtd@lists.infradead.org,
	Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
	linux-arm-kernel@lists.infradead.org,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 02 Mar 2015 17:52:35 +0100	[thread overview]
Message-ID: <54F49553.2020307@free-electrons.com> (raw)
In-Reply-To: <20150228090122.GA11148@brian-ubuntu>

On 28/02/2015 10:01, Brian Norris wrote:
> On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote:
>> The NDDB register holds the data that are needed by the read and write
>> commands.
>>
>> However, during a read PIO access, the datasheet specifies that after each 32
>> bytes read in that register, when BCH is enabled, we have to make sure that the
>> RDDREQ bit is set in the NDSR register.
>>
>> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
>> SoCs, when a read on a newly erased page would end up in the driver reporting a
>> timeout from the NAND.
>>
>> Cc: <stable@vger.kernel.org> # v3.14
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Pushed this one to linux-mtd.git. I'll try to get it out in the 4.0
> cycle. I assume patch 2 (the DT addition) will go through arm-soc.

Yes, now that you took the driver part,  I will apply it on mvebu and then push it
to arm-soc.

Thanks,

Gregory


> 
> Brian
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

WARNING: multiple messages have this Message-ID (diff)
From: gregory.clement@free-electrons.com (Gregory CLEMENT)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 02 Mar 2015 17:52:35 +0100	[thread overview]
Message-ID: <54F49553.2020307@free-electrons.com> (raw)
In-Reply-To: <20150228090122.GA11148@brian-ubuntu>

On 28/02/2015 10:01, Brian Norris wrote:
> On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote:
>> The NDDB register holds the data that are needed by the read and write
>> commands.
>>
>> However, during a read PIO access, the datasheet specifies that after each 32
>> bytes read in that register, when BCH is enabled, we have to make sure that the
>> RDDREQ bit is set in the NDSR register.
>>
>> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
>> SoCs, when a read on a newly erased page would end up in the driver reporting a
>> timeout from the NAND.
>>
>> Cc: <stable@vger.kernel.org> # v3.14
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Pushed this one to linux-mtd.git. I'll try to get it out in the 4.0
> cycle. I assume patch 2 (the DT addition) will go through arm-soc.

Yes, now that you took the driver part,  I will apply it on mvebu and then push it
to arm-soc.

Thanks,

Gregory


> 
> Brian
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

WARNING: multiple messages have this Message-ID (diff)
From: Gregory CLEMENT <gregory.clement@free-electrons.com>
To: Brian Norris <computersforpeace@gmail.com>,
	Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
	linux-mtd@lists.infradead.org,
	Boris Brezillon <boris@free-electrons.com>,
	Thomas Petazzoni <thomas@free-electrons.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Tawfik Bayouk <tawfik@marvell.com>,
	Nadav Haklai <nadavh@marvell.com>,
	Lior Amsalem <alior@marvell.com>,
	Sudhakar Gundubogula <sudhakar@marvell.com>,
	Seif Mazareeb <seif@marvell.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 02 Mar 2015 17:52:35 +0100	[thread overview]
Message-ID: <54F49553.2020307@free-electrons.com> (raw)
In-Reply-To: <20150228090122.GA11148@brian-ubuntu>

On 28/02/2015 10:01, Brian Norris wrote:
> On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote:
>> The NDDB register holds the data that are needed by the read and write
>> commands.
>>
>> However, during a read PIO access, the datasheet specifies that after each 32
>> bytes read in that register, when BCH is enabled, we have to make sure that the
>> RDDREQ bit is set in the NDSR register.
>>
>> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
>> SoCs, when a read on a newly erased page would end up in the driver reporting a
>> timeout from the NAND.
>>
>> Cc: <stable@vger.kernel.org> # v3.14
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Pushed this one to linux-mtd.git. I'll try to get it out in the 4.0
> cycle. I assume patch 2 (the DT addition) will go through arm-soc.

Yes, now that you took the driver part,  I will apply it on mvebu and then push it
to arm-soc.

Thanks,

Gregory


> 
> Brian
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

  reply	other threads:[~2015-03-02 16:52 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-18 10:32 [PATCH v4 0/2] ARM: mvebu: a385-db-ap: Enable the NAND controller Maxime Ripard
2015-02-18 10:32 ` Maxime Ripard
2015-02-18 10:32 ` Maxime Ripard
2015-02-18 10:32 ` [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining Maxime Ripard
2015-02-18 10:32   ` Maxime Ripard
2015-02-18 10:32   ` Maxime Ripard
2015-02-18 12:52   ` Boris Brezillon
2015-02-18 12:52     ` Boris Brezillon
2015-02-18 12:52     ` Boris Brezillon
2015-02-18 13:40   ` Ezequiel Garcia
2015-02-18 13:40     ` Ezequiel Garcia
2015-02-18 13:40     ` Ezequiel Garcia
2015-02-18 13:40     ` Ezequiel Garcia
2015-02-18 14:01     ` Maxime Ripard
2015-02-18 14:01       ` Maxime Ripard
2015-02-18 14:01       ` Maxime Ripard
2015-02-18 14:06       ` Ezequiel Garcia
2015-02-18 14:06         ` Ezequiel Garcia
2015-02-18 14:06         ` Ezequiel Garcia
2015-02-18 14:06         ` Ezequiel Garcia
2015-02-28  9:01   ` Brian Norris
2015-02-28  9:01     ` Brian Norris
2015-02-28  9:01     ` Brian Norris
2015-03-02 16:52     ` Gregory CLEMENT [this message]
2015-03-02 16:52       ` Gregory CLEMENT
2015-03-02 16:52       ` Gregory CLEMENT
2015-02-18 10:32 ` [PATCH v4 2/2] ARM: mvebu: a385-db-ap: Enable the NAND Maxime Ripard
2015-02-18 10:32   ` Maxime Ripard
2015-02-18 10:32   ` Maxime Ripard
2015-03-03  8:10   ` Gregory CLEMENT
2015-03-03  8:10     ` Gregory CLEMENT
2015-03-03  8:10     ` Gregory CLEMENT
2015-03-03  9:57     ` Maxime Ripard
2015-03-03  9:57       ` Maxime Ripard
2015-03-03  9:57       ` Maxime Ripard

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=54F49553.2020307@free-electrons.com \
    --to=gregory.clement@free-electrons.com \
    --cc=alior@marvell.com \
    --cc=andrew@lunn.ch \
    --cc=boris@free-electrons.com \
    --cc=computersforpeace@gmail.com \
    --cc=ezequiel.garcia@free-electrons.com \
    --cc=jason@lakedaemon.net \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=maxime.ripard@free-electrons.com \
    --cc=nadavh@marvell.com \
    --cc=sebastian.hesselbarth@gmail.com \
    --cc=seif@marvell.com \
    --cc=stable@vger.kernel.org \
    --cc=sudhakar@marvell.com \
    --cc=tawfik@marvell.com \
    --cc=thomas@free-electrons.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.