From: Paolo Bonzini <pbonzini@redhat.com>
To: Avi Kivity <avi.kivity@gmail.com>, Nadav Amit <nadav.amit@gmail.com>
Cc: "kvm list" <kvm@vger.kernel.org>, "Radim Krčmář" <rkrcmar@redhat.com>
Subject: Re: 2 CPU Conformance Issue in KVM/x86
Date: Mon, 09 Mar 2015 20:38:51 +0100 [thread overview]
Message-ID: <54FDF6CB.8050209@redhat.com> (raw)
In-Reply-To: <54FDF241.8080002@gmail.com>
On 09/03/2015 20:19, Avi Kivity wrote:
> I can't think of one with reasonable performance either. Perhaps the
> maintainers could raise the issue with Intel. It looks academic but it
> can happen in real life -- KVM for example used to rely on reserved bits
> faults (it set all bits in the PTE so it wouldn't have been caught by
> this).
Yes, and it checked that MAXPHYADDR != 52 before. If you want to set
only one bit, making that bit 51 makes sense anyway for simplicity, so
it is still 99.9% academic. Once processors appear with MAXPHYADDR =
52, the remaining 0.1% will become more relevant.
The current limit is IIRC 46 or 48 (on Haswell Xeons).
Paolo
next prev parent reply other threads:[~2015-03-09 19:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-03 8:34 2 CPU Conformance Issue in KVM/x86 Nadav Amit
2015-03-03 9:52 ` Paolo Bonzini
2015-03-03 10:18 ` Nadav Amit
2015-03-03 14:31 ` Radim Krčmář
2015-03-09 17:08 ` Avi Kivity
2015-03-09 17:51 ` Nadav Amit
2015-03-09 18:23 ` Avi Kivity
2015-03-09 19:07 ` Nadav Amit
2015-03-09 19:19 ` Avi Kivity
2015-03-09 19:38 ` Paolo Bonzini [this message]
2015-03-09 19:49 ` Avi Kivity
2015-03-10 10:47 ` Paolo Bonzini
2015-03-10 20:38 ` Avi Kivity
2015-03-09 19:33 ` Paolo Bonzini
2015-03-09 19:50 ` Avi Kivity
2015-03-10 10:44 ` Paolo Bonzini
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