From: Markos Chandras <Markos.Chandras@imgtec.com>
To: David Daney <ddaney.cavm@gmail.com>, <linux-mips@linux-mips.org>,
<ralf@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>,
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>,
David Daney <david.daney@cavium.com>
Subject: Re: [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction"
Date: Wed, 11 Mar 2015 08:28:55 +0000 [thread overview]
Message-ID: <54FFFCC7.5090707@imgtec.com> (raw)
In-Reply-To: <1424731974-27926-1-git-send-email-ddaney.cavm@gmail.com>
On 02/23/2015 10:52 PM, David Daney wrote:
> From: David Daney <david.daney@cavium.com>
>
> This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.
>
> There are two problems:
>
> 1) It breaks OCTEON, which will now crash in early boot with:
>
> Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
>
> 2) The logic is broken.
>
> The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
> is required. The offending patch attempts (and fails) to change the
> meaning to be that EHB is part of the ISA.
>
> Signed-off-by: David Daney <david.daney@cavium.com>
> ---
Hi,
First of all sorry about the octeon breakage.
However, whilst this patch will fix Octeon it will break R6
Can we please consider another patch that will simply use
cpu_has_mips_r2_r6 instead of cpu_has_mips_r2 so both will work in 4.0?
--
markos
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <Markos.Chandras@imgtec.com>
To: David Daney <ddaney.cavm@gmail.com>,
linux-mips@linux-mips.org, ralf@linux-mips.org
Cc: linux-kernel@vger.kernel.org,
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>,
David Daney <david.daney@cavium.com>
Subject: Re: [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction"
Date: Wed, 11 Mar 2015 08:28:55 +0000 [thread overview]
Message-ID: <54FFFCC7.5090707@imgtec.com> (raw)
Message-ID: <20150311082855.WTRinBUgoffc_7XrlKicxBOmtayX8YI43dN0DHMQoqQ@z> (raw)
In-Reply-To: <1424731974-27926-1-git-send-email-ddaney.cavm@gmail.com>
On 02/23/2015 10:52 PM, David Daney wrote:
> From: David Daney <david.daney@cavium.com>
>
> This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.
>
> There are two problems:
>
> 1) It breaks OCTEON, which will now crash in early boot with:
>
> Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
>
> 2) The logic is broken.
>
> The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
> is required. The offending patch attempts (and fails) to change the
> meaning to be that EHB is part of the ISA.
>
> Signed-off-by: David Daney <david.daney@cavium.com>
> ---
Hi,
First of all sorry about the octeon breakage.
However, whilst this patch will fix Octeon it will break R6
Can we please consider another patch that will simply use
cpu_has_mips_r2_r6 instead of cpu_has_mips_r2 so both will work in 4.0?
--
markos
next prev parent reply other threads:[~2015-03-11 8:29 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-23 22:52 [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction" David Daney
2015-02-24 1:10 ` Maciej W. Rozycki
2015-03-11 8:28 ` Markos Chandras [this message]
2015-03-11 8:28 ` Markos Chandras
2015-03-11 16:51 ` David Daney
2015-03-13 9:18 ` [PATCH] MIPS: mm: tlbex: Replace cpu_has_mips_r2_exec_hazard with cpu_has_mips_r2_r6 Markos Chandras
2015-03-13 9:18 ` Markos Chandras
2015-03-13 14:44 ` Ralf Baechle
2015-03-13 15:41 ` Markos Chandras
2015-03-13 15:41 ` Markos Chandras
2015-03-26 20:52 ` Maciej W. Rozycki
2015-03-13 15:46 ` David Daney
2015-03-13 15:46 ` David Daney
2015-03-13 17:10 ` Ralf Baechle
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