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From: Julien Grall <julien.grall@arm.com>
To: Manish Jaggi <mjaggi@caviumnetworks.com>,
	Julien Grall <julien.grall@gmail.com>,
	Stefano Stabellini <sstabellini@kernel.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	andre.przywara@arm.com, xen-devel@lists.xenproject.org,
	Manish Jaggi <manish.jaggi@cavium.com>
Subject: Re: [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps
Date: Tue, 3 Apr 2018 16:33:48 +0100	[thread overview]
Message-ID: <54e635d0-c261-a2ee-e885-ed13d16bc707@arm.com> (raw)
In-Reply-To: <dae0d8c0-51dc-af1f-d60a-c1a611c33fa6@caviumnetworks.com>

Hi,

On 28/03/18 04:48, Manish Jaggi wrote:
> 
> 
> On 03/28/2018 06:18 AM, Julien Grall wrote:
>>
>> Hi,
>>
>> Sorry for the formatting.
>>
>> On Wed, 28 Mar 2018, 04:18 Stefano Stabellini, <sstabellini@kernel.org 
>> <mailto:sstabellini@kernel.org>> wrote:
>>
>>     On Tue, 27 Mar 2018, Marc Zyngier wrote:
>>     > On 27/03/18 11:10, Manish Jaggi wrote:
>>     > >
>>     > >
>>     > > On 03/27/2018 03:31 PM, Marc Zyngier wrote:
>>     > >> On 27/03/18 10:07, Manish Jaggi wrote:
>>     > >>> The errata will require to emulate the GIC virtual CPU
>>     interface in Xen.
>>     > >>> Because the hypervisor will update its internal state of the
>>     vGIC, we want
>>     > >>> to avoid messing up with it. So the errata is handled
>>     separately from the
>>     > >>> rest of the hypervisor.
>>     > >>>
>>     > >>> New file vgic-v3-sr.c is added which will hold trap and
>>     emulate code
>>     > >>> for group0 / group1 registers. Workaround for cavium Errata
>>     30115
>>     > >>> needs this emulation code.
>>     > >>>
>>     > >>> vgic_v3_handle_cpuif_access would be called from
>>     do_trap_guest_sync
>>     > >>> in subsequent patches based on errata macros.
>>     > >>>
>>     > >>> Signed-off-by: Manish Jaggi <manish.jaggi@cavium.com
>>     <mailto:manish.jaggi@cavium.com>>
>>     > >>> ---
>>     > >>>   xen/arch/arm/arm64/vgic-v3-sr.c   | 60
>>     +++++++++++++++++++++++++++++++++++++++
>>     > >>>   xen/include/asm-arm/arm64/traps.h |  2 ++
>>     > >>>   2 files changed, 62 insertions(+)
>>     > >>>   create mode 100644 xen/arch/arm/arm64/vgic-v3-sr.c
>>     > >>>
>>     > >>> diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c
>>     b/xen/arch/arm/arm64/vgic-v3-sr.c
>>     > >>> new file mode 100644
>>     > >>> index 0000000000..39ab1ed6ca
>>     > >>> --- /dev/null
>>     > >>> +++ b/xen/arch/arm/arm64/vgic-v3-sr.c
>>     > >>> @@ -0,0 +1,60 @@
>>     > >>> +/*
>>     > >>> + * xen/arch/arm/arm64/vgic-v3-sr.c
>>     > >>> + *
>>     > >>> + * Code to emulate group0/group1 traps for handling
>>     > >>> + * cavium erratum 30115
>>     > >>> + *
>>     > >>> + * Manish Jaggi <manish.jaggi@cavium.com
>>     <mailto:manish.jaggi@cavium.com>>
>>     > >>> + * Copyright (c) 2018 Cavium.
>>     > >> IANAL, but I don't think this copyright notice is correct.
>>     > >>
>>     > >> I wrote about 90% of this series, and the copyright for that
>>     code is
>>     > >> owned by ARM, and licensed under the GPLv2. You have the right to
>>     > >> duplicate that code and do almost whatever you want with
>>     (within the
>>     > >> limits of the GPLv2), but you still don't own the copyright.
>>     > >>
>>     > >> I suggest you get in touch with your legal department for
>>     clarification
>>     > >> on the matter.
>>     > > I will remove the copyright line, and add this
>>     > > Original Author: Marc Zyngier <>
>>     > > Ported to Xen by: Manish Jaggi <>
>>     >
>>     > You're missing the point. I don't give a damn about the
>>     authorship (I'm
>>     > not exactly proud to have written that code).
>>
>>     :-D
>>
>>     > The problem at hand is the
>>     > ARM copyright, which should be preserved (as no-one in Cavium
>>     wrote a
>>     > single line of the original code).
>>
>>     I have been asking myself similar questions for a while now when we
>>     import code from Linux. The copyright/author line at the top of
>>     the file
>>     is somewhat arbitrary as every person that touched the code has
>>     copyright over her modifications. This is why at some point I
>>     thought we
>>     had to retain the full list of Signed-off-by lines that ever
>>     touched the
>>     code in question, but then, reading the DCO terms one more time:
>>
>>      (b) The contribution is based upon previous work that, to the best
>>          of my knowledge, is covered under an appropriate open source
>>          license and I have the right under that license to submit that
>>          work with modifications, whether created in whole or in part
>>          by me, under the same open source license (unless I am
>>          permitted to submit under a different license), as indicated
>>          in the file; or
>>
>>     I checked in the Linux kernel when code was imported from the Xen
>>     hypervisor to KVM a long time ago, and only a singled Signed-off-by of
>>     the person importing the code was used.
>>
>>
>> It does not mean it was a good practice ;).
>>
>>
>>     This is how I came to the conclusion that actually we don't need to do
>>     anything special, although it would be nice as a courtesy to
>>     retain the
>>     copyright/author lines at the top of the file. It would also be
>>     nice to
>>     have the original Linux commit id in the commit message to help
>>     tracking
>>     the history.
>>
>>
>> We had a similar discussion on the spectre patches a couple of months 
>> ago. The original author is useful to know if we need to relicense 
>> some files.
>>
>> Having just the commit id from Linux would create more overhead.
>>
>> Lars suggested to create a file listing where all the work come from. 
>> For commit, I think it would be ok to just add the Signed-off in the 
>> commit and retain copyright in the code.
>>
>> Of course, it is ok add the Cavium one if code is changed. But no 
>> copyright should be dropped.
>>
> How about
> 
> +/*
> + * xen/arch/arm/arm64/vgic-v3-sr.c
> + *
> + * Code to emulate group0/group1 traps for handling
> + * cavium erratum 30115
> + *
> + * This file merges code from Linux virt/kvm/arm/hyp/vgic-v3-sr.c
> + * Copyright (C) 2012-2015 - ARM Ltd
> + * Original Author: Marc Zyngier <marc.zyngier@arm.com>
> + * Code Ported to Xen by: Manish Jaggi <manish.jaggi@cavium.com>
> ...

That would be ok for me.

Cheers,

-- 
Julien Grall

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  reply	other threads:[~2018-04-03 15:33 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-27  9:07 [PATCH v2 00/17] arm64: Mediate access to GICv3 sysregs at EL2 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps Manish Jaggi
2018-03-27 10:01   ` Marc Zyngier
2018-03-27 10:10     ` Manish Jaggi
2018-03-27 10:22       ` Marc Zyngier
2018-03-27 20:16         ` Stefano Stabellini
2018-03-28  0:48           ` Julien Grall
2018-03-28  3:48             ` Manish Jaggi
2018-04-03 15:33               ` Julien Grall [this message]
2018-03-27  9:07 ` [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler Manish Jaggi
2018-03-27 10:30   ` Marc Zyngier
2018-03-27 10:35     ` Manish Jaggi
2018-03-27 10:45       ` Marc Zyngier
2018-03-27 10:56         ` Manish Jaggi
2018-03-27 11:05           ` Marc Zyngier
2018-03-27 11:07             ` Manish Jaggi
2018-03-27 11:11               ` Marc Zyngier
2018-03-27 11:15                 ` Manish Jaggi
2018-03-27 11:25                   ` Marc Zyngier
2018-03-27 11:27                     ` Manish Jaggi
2018-03-27 11:38                       ` Marc Zyngier
2018-03-28  3:51                         ` Manish Jaggi
2018-04-03 15:59                           ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 03/17] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 04/17] arm64: Add accessors for the ICH_APxRn_EL2 registers Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 05/17] Expose ich_read/write_lr in vgic-v3-sr.c Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 06/17] arm64: Add ICV_IAR1_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Manish Jaggi
2018-03-27 10:18   ` Marc Zyngier
2018-04-02 11:03     ` Manish Jaggi
2018-04-02 11:17       ` Manish Jaggi
2018-04-05  9:40         ` Julien Grall
2018-04-05 19:53           ` Stefano Stabellini
2018-04-06  8:37           ` Manish Jaggi
2018-04-11 14:16             ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 08/17] arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 09/17] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler Manish Jaggi
2018-03-27 10:56   ` Marc Zyngier
2018-03-27 11:02     ` Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 10/17] arm64: vgic-v3: Add ICV_BPR0_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 11/17] arm64: vgic-v3: Add ICV_IGRPEN0_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers Manish Jaggi
2018-03-27 10:58   ` Marc Zyngier
2018-03-27 11:01     ` Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 13/17] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 14/17] arm64: Add config for Cavium Thunder erratum 30115 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 15/17] arm: Hook workaround handler from traps.c based on Cavium workaround_30115 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 16/17] arm64: if trapping a write-to-read-only GICv3 access inject Undef exception in guest Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 17/17] arm64: if trapping a read-from-write-only GICv3 access inject undef " Manish Jaggi

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