From: James Sullivan <sullivan.james.f@gmail.com>
To: Jan Kiszka <jan.kiszka@siemens.com>, kvm@vger.kernel.org
Cc: gleb@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com
Subject: Re: [PATCH v3 0/2] kvm: x86: Implement handling of RH=1 for MSI delivery in KVM
Date: Tue, 17 Mar 2015 09:33:26 -0600 [thread overview]
Message-ID: <55084946.7090106@gmail.com> (raw)
In-Reply-To: <5507E376.7020305@siemens.com>
On 03/17/2015 02:19 AM, Jan Kiszka wrote:
>
> Once the kernel side is settled, would you mind looking into equivalent
> support for QEMU's APIC as well? Just to keep it easy to switch between
> both modes without too many functional restrictions.
>
> Thanks!
> Jan
>
Good idea! I'm hoping to participate in GSoC working on shunting some interrupt
handling devices out of the KVM and into QEMU, so that's definitely something
I'll start to look into.
-James
next prev parent reply other threads:[~2015-03-17 15:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-17 1:30 [PATCH v3 0/2] kvm: x86: Implement handling of RH=1 for MSI delivery in KVM James Sullivan
2015-03-17 1:30 ` [PATCH v3 1/2] kvm: x86: Extended struct kvm_lapic_irq with msi_redir_hint for MSI delivery James Sullivan
2015-03-17 14:02 ` Radim Krčmář
2015-03-17 1:30 ` [PATCH v3 2/2] kvm: x86: Deliver MSI IRQ to only lowest prio cpu if msi_redir_hint is true James Sullivan
2015-03-17 14:18 ` Radim Krčmář
2015-03-17 8:19 ` [PATCH v3 0/2] kvm: x86: Implement handling of RH=1 for MSI delivery in KVM Jan Kiszka
2015-03-17 15:33 ` James Sullivan [this message]
2015-03-29 2:17 ` James Sullivan
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