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From: Archit Taneja <architt@codeaurora.org>
To: Stephane Viau <sviau@codeaurora.org>, dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines
Date: Mon, 23 Mar 2015 16:20:46 +0530	[thread overview]
Message-ID: <550FF006.6090600@codeaurora.org> (raw)
In-Reply-To: <1426276174-17010-4-git-send-email-sviau@codeaurora.org>

Hi Stephane,

On 03/14/2015 01:19 AM, Stephane Viau wrote:
> Some interfaces (WB, DSI Command Mode) need to be kicked off
> through a START Signal. This signal needs to be sent at the right
> time and requests in some cases to keep track of the pipeline
> status (eg: whether pipeline registers are flushed AND output WB
> buffers are ready, in case of WB interface).
>
> Signed-off-by: Stephane Viau <sviau@codeaurora.org>
> ---
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c     |   2 +
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h     |   7 +-
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c    |  31 ++--
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c     | 247 ++++++++++++++++++++++++----
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h     |  72 +++-----
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  13 +-
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h     |   1 +
>   7 files changed, 276 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> index c078f30..72c075a 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = {
>   	.ctl = {
>   		.count = 5,
>   		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
> +		.flush_hw_mask = 0x0003ffff,
>   	},
>   	.pipe_vig = {
>   		.count = 3,
> @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = {
>   	.ctl = {
>   		.count = 5,
>   		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
> +		.flush_hw_mask = 0x003fffff,

msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I'm 
not wrong. Could you please add it for the next revision, or as a part 
of the 8x16 hw cfg patch?

Thanks,
Archit

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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WARNING: multiple messages have this Message-ID (diff)
From: Archit Taneja <architt@codeaurora.org>
To: Stephane Viau <sviau@codeaurora.org>, dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	robdclark@gmail.com
Subject: Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines
Date: Mon, 23 Mar 2015 16:20:46 +0530	[thread overview]
Message-ID: <550FF006.6090600@codeaurora.org> (raw)
In-Reply-To: <1426276174-17010-4-git-send-email-sviau@codeaurora.org>

Hi Stephane,

On 03/14/2015 01:19 AM, Stephane Viau wrote:
> Some interfaces (WB, DSI Command Mode) need to be kicked off
> through a START Signal. This signal needs to be sent at the right
> time and requests in some cases to keep track of the pipeline
> status (eg: whether pipeline registers are flushed AND output WB
> buffers are ready, in case of WB interface).
>
> Signed-off-by: Stephane Viau <sviau@codeaurora.org>
> ---
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c     |   2 +
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h     |   7 +-
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c    |  31 ++--
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c     | 247 ++++++++++++++++++++++++----
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h     |  72 +++-----
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  13 +-
>   drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h     |   1 +
>   7 files changed, 276 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> index c078f30..72c075a 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = {
>   	.ctl = {
>   		.count = 5,
>   		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
> +		.flush_hw_mask = 0x0003ffff,
>   	},
>   	.pipe_vig = {
>   		.count = 3,
> @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = {
>   	.ctl = {
>   		.count = 5,
>   		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
> +		.flush_hw_mask = 0x003fffff,

msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I'm 
not wrong. Could you please add it for the next revision, or as a part 
of the 8x16 hw cfg patch?

Thanks,
Archit

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2015-03-23 10:50 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-03 18:36 [PATCH 0/4] drm/msm: preparation for WB/DSI connectors Stephane Viau
2015-03-03 18:36 ` [PATCH 1/4] drm/msm/mdp5: Update generated header files Stephane Viau
2015-03-03 18:36   ` Stephane Viau
2015-03-03 18:37   ` [PATCH] rnndb: Prepare for more interfaces support (WB, DSI) Stephane Viau
2015-03-03 18:37     ` Stephane Viau
2015-03-03 18:36 ` [PATCH 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Stephane Viau
2015-03-03 18:36   ` Stephane Viau
2015-03-04  6:22   ` Archit Taneja
2015-03-04  6:22     ` Archit Taneja
2015-03-03 18:36 ` [PATCH 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines Stephane Viau
2015-03-03 18:36   ` Stephane Viau
2015-03-03 18:36 ` [PATCH 4/4] drm/msm/mdp5: Make the intf connection in config module Stephane Viau
2015-03-03 18:36   ` Stephane Viau
2015-03-04  6:13   ` Archit Taneja
2015-03-04  6:13     ` Archit Taneja
2015-03-04 15:44     ` "Stéphane Viau"
2015-03-04 15:44       ` "Stéphane Viau"
2015-03-05  4:03       ` Archit Taneja
2015-03-05 14:59 ` [PATCH v2 0/4] drm/msm: preparation for WB/DSI connectors Stephane Viau
2015-03-05 14:59   ` [PATCH v2 1/4] drm/msm/mdp5: Update generated header files Stephane Viau
2015-03-05 14:59     ` Stephane Viau
2015-03-05 14:59   ` [PATCH v2 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Stephane Viau
2015-03-05 14:59     ` Stephane Viau
2015-03-05 14:59   ` [PATCH v2 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines Stephane Viau
2015-03-05 14:59   ` [PATCH v2 4/4] drm/msm/mdp5: Make the intf connection in config module Stephane Viau
2015-03-05 14:59     ` Stephane Viau
2015-03-09 13:11 ` [PATCH 0/5] drm/msm: Add display configuration for msm8x16 Stephane Viau
2015-03-09 13:11   ` [PATCH 1/5] drm/msm/mdp5: Update headers (introduce MDP5 domain) Stephane Viau
2015-03-09 13:11   ` [PATCH 2/5] drm/msm/mdp5: Separate MDP5 domain from MDSS domain Stephane Viau
2015-03-09 13:11   ` [PATCH 3/5] drm/msm/mdp5: Update headers (remove enum mdp5_client_id) Stephane Viau
2015-03-09 13:11   ` [PATCH 4/5] drm/msm/mdp5: Get SMP client list from mdp5_cfg Stephane Viau
2015-03-09 13:11   ` [PATCH 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16 Stephane Viau
2015-03-12  9:04     ` Archit Taneja
2015-03-12  9:04       ` Archit Taneja
2015-03-13 19:45       ` "Stéphane Viau"
2015-03-13 19:49         ` [PATCH v3 0/4] drm/msm: preparation for WB/DSI connectors Stephane Viau
2015-03-13 19:49           ` [PATCH v3 1/4] drm/msm/mdp5: Update generated header files Stephane Viau
2015-03-13 19:49             ` Stephane Viau
2015-03-13 19:49           ` [PATCH v3 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Stephane Viau
2015-03-13 19:49           ` [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines Stephane Viau
2015-03-13 19:49             ` Stephane Viau
2015-03-23 10:50             ` Archit Taneja [this message]
2015-03-23 10:50               ` Archit Taneja
2015-03-23 22:10               ` "Stéphane Viau"
2015-03-23 22:10                 ` "Stéphane Viau"
2015-03-24  4:47                 ` Archit Taneja
2015-03-13 19:49           ` [PATCH v3 4/4] drm/msm/mdp5: Make the intf connection in config module Stephane Viau
2015-03-13 19:49             ` Stephane Viau
2015-03-16  5:03         ` [PATCH 5/5] drm/msm/mdp5: Add hardware configuration for msm8x16 Archit Taneja
2015-03-16  5:03           ` Archit Taneja
2015-03-09 13:12   ` [PATCH 1/2] rnndb: Separate MDP5 domain from MDSS domain Stephane Viau
2015-03-09 13:12     ` [PATCH 2/2] rnndb: Do not use enum mdp5_client_id to configure SMP Stephane Viau

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