[PATCH 0/3] mips: OCTEON: Support for little-endian mode

[PATCH 0/3] mips: OCTEON: Support for little-endian mode

[Aleksey Makarov]

These patches enable compiling and booting kernel on Octeon boards
in little-endian mode.

David Daney (3):
  MIPS: OCTEON: Handle bootloader structures in little-endian mode.
  MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h
  MIPS: OCTEON: Enable little endian kernel.

 arch/mips/Kconfig                                  |  3 +-
 arch/mips/cavium-octeon/octeon_boot.h              | 23 +++++++
 .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 ++++++++++++++++++++++
 arch/mips/include/asm/octeon/cvmx-bootinfo.h       | 55 ++++++++++++++++
 4 files changed, 154 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/mangle-port.h

-- 
2.3.3

[PATCH 0/3] mips: OCTEON: Support for little-endian mode

[Aleksey Makarov]

These patches enable compiling and booting kernel on Octeon boards
in little-endian mode.

David Daney (3):
  MIPS: OCTEON: Handle bootloader structures in little-endian mode.
  MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h
  MIPS: OCTEON: Enable little endian kernel.

 arch/mips/Kconfig                                  |  3 +-
 arch/mips/cavium-octeon/octeon_boot.h              | 23 +++++++
 .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 ++++++++++++++++++++++
 arch/mips/include/asm/octeon/cvmx-bootinfo.h       | 55 ++++++++++++++++
 4 files changed, 154 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/mangle-port.h

-- 
2.3.3

[PATCH 1/3] MIPS: OCTEON: Handle bootloader structures in little-endian mode.

[Aleksey Makarov]

From: David Daney <david.daney@cavium.com>

Compensate for the differences in the layout of in-memory bootloader
information as seen from little-endian mode.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
---
 arch/mips/cavium-octeon/octeon_boot.h        | 23 ++++++++++++
 arch/mips/include/asm/octeon/cvmx-bootinfo.h | 55 ++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 7b066bb..a6ce7c4 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -37,11 +37,13 @@ struct boot_init_vector {
 
 /* similar to bootloader's linux_app_boot_info but without global data */
 struct linux_app_boot_info {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t labi_signature;
 	uint32_t start_core0_addr;
 	uint32_t avail_coremask;
 	uint32_t pci_console_active;
 	uint32_t icache_prefetch_disable;
+	uint32_t padding;
 	uint64_t InitTLBStart_addr;
 	uint32_t start_app_addr;
 	uint32_t cur_exception_base;
@@ -49,6 +51,27 @@ struct linux_app_boot_info {
 	uint32_t compact_flash_common_base_addr;
 	uint32_t compact_flash_attribute_base_addr;
 	uint32_t led_display_base_addr;
+#else
+	uint32_t start_core0_addr;
+	uint32_t labi_signature;
+
+	uint32_t pci_console_active;
+	uint32_t avail_coremask;
+
+	uint32_t padding;
+	uint32_t icache_prefetch_disable;
+
+	uint64_t InitTLBStart_addr;
+
+	uint32_t cur_exception_base;
+	uint32_t start_app_addr;
+
+	uint32_t compact_flash_common_base_addr;
+	uint32_t no_mark_private_data;
+
+	uint32_t led_display_base_addr;
+	uint32_t compact_flash_attribute_base_addr;
+#endif
 };
 
 /* If not to copy a lot of bootloader's structures
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 2298199..c373d95 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -53,6 +53,7 @@
  * to 0.
  */
 struct cvmx_bootinfo {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t major_version;
 	uint32_t minor_version;
 
@@ -123,6 +124,60 @@ struct cvmx_bootinfo {
 	 */
 	uint64_t fdt_addr;
 #endif
+#else				/* __BIG_ENDIAN */
+	/*
+	 * Little-Endian: When the CPU mode is switched to
+	 * little-endian, the view of the structure has some of the
+	 * fields swapped.
+	 */
+	uint32_t minor_version;
+	uint32_t major_version;
+
+	uint64_t stack_top;
+	uint64_t heap_base;
+	uint64_t heap_end;
+	uint64_t desc_vaddr;
+
+	uint32_t stack_size;
+	uint32_t exception_base_addr;
+
+	uint32_t core_mask;
+	uint32_t flags;
+
+	uint32_t phy_mem_desc_addr;
+	uint32_t dram_size;
+
+	uint32_t eclock_hz;
+	uint32_t debugger_flags_base_addr;
+
+	uint32_t reserved0;
+	uint32_t dclock_hz;
+
+	uint8_t reserved3;
+	uint8_t reserved2;
+	uint16_t reserved1;
+	uint8_t board_rev_minor;
+	uint8_t board_rev_major;
+	uint16_t board_type;
+
+	char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+	uint8_t mac_addr_base[6];
+	uint8_t mac_addr_count;
+	uint8_t pad[5];
+
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+	uint64_t compact_flash_common_base_addr;
+	uint64_t compact_flash_attribute_base_addr;
+	uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+	uint32_t config_flags;
+	uint32_t dfa_ref_clock_hz;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+	uint64_t fdt_addr;
+#endif
+#endif
 };
 
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST			(1ull << 0)
-- 
2.3.3

[PATCH 1/3] MIPS: OCTEON: Handle bootloader structures in little-endian mode.

[Aleksey Makarov]

From: David Daney <david.daney@cavium.com>

Compensate for the differences in the layout of in-memory bootloader
information as seen from little-endian mode.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
---
 arch/mips/cavium-octeon/octeon_boot.h        | 23 ++++++++++++
 arch/mips/include/asm/octeon/cvmx-bootinfo.h | 55 ++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 7b066bb..a6ce7c4 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -37,11 +37,13 @@ struct boot_init_vector {
 
 /* similar to bootloader's linux_app_boot_info but without global data */
 struct linux_app_boot_info {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t labi_signature;
 	uint32_t start_core0_addr;
 	uint32_t avail_coremask;
 	uint32_t pci_console_active;
 	uint32_t icache_prefetch_disable;
+	uint32_t padding;
 	uint64_t InitTLBStart_addr;
 	uint32_t start_app_addr;
 	uint32_t cur_exception_base;
@@ -49,6 +51,27 @@ struct linux_app_boot_info {
 	uint32_t compact_flash_common_base_addr;
 	uint32_t compact_flash_attribute_base_addr;
 	uint32_t led_display_base_addr;
+#else
+	uint32_t start_core0_addr;
+	uint32_t labi_signature;
+
+	uint32_t pci_console_active;
+	uint32_t avail_coremask;
+
+	uint32_t padding;
+	uint32_t icache_prefetch_disable;
+
+	uint64_t InitTLBStart_addr;
+
+	uint32_t cur_exception_base;
+	uint32_t start_app_addr;
+
+	uint32_t compact_flash_common_base_addr;
+	uint32_t no_mark_private_data;
+
+	uint32_t led_display_base_addr;
+	uint32_t compact_flash_attribute_base_addr;
+#endif
 };
 
 /* If not to copy a lot of bootloader's structures
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 2298199..c373d95 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -53,6 +53,7 @@
  * to 0.
  */
 struct cvmx_bootinfo {
+#ifdef __BIG_ENDIAN_BITFIELD
 	uint32_t major_version;
 	uint32_t minor_version;
 
@@ -123,6 +124,60 @@ struct cvmx_bootinfo {
 	 */
 	uint64_t fdt_addr;
 #endif
+#else				/* __BIG_ENDIAN */
+	/*
+	 * Little-Endian: When the CPU mode is switched to
+	 * little-endian, the view of the structure has some of the
+	 * fields swapped.
+	 */
+	uint32_t minor_version;
+	uint32_t major_version;
+
+	uint64_t stack_top;
+	uint64_t heap_base;
+	uint64_t heap_end;
+	uint64_t desc_vaddr;
+
+	uint32_t stack_size;
+	uint32_t exception_base_addr;
+
+	uint32_t core_mask;
+	uint32_t flags;
+
+	uint32_t phy_mem_desc_addr;
+	uint32_t dram_size;
+
+	uint32_t eclock_hz;
+	uint32_t debugger_flags_base_addr;
+
+	uint32_t reserved0;
+	uint32_t dclock_hz;
+
+	uint8_t reserved3;
+	uint8_t reserved2;
+	uint16_t reserved1;
+	uint8_t board_rev_minor;
+	uint8_t board_rev_major;
+	uint16_t board_type;
+
+	char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+	uint8_t mac_addr_base[6];
+	uint8_t mac_addr_count;
+	uint8_t pad[5];
+
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+	uint64_t compact_flash_common_base_addr;
+	uint64_t compact_flash_attribute_base_addr;
+	uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+	uint32_t config_flags;
+	uint32_t dfa_ref_clock_hz;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+	uint64_t fdt_addr;
+#endif
+#endif
 };
 
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST			(1ull << 0)
-- 
2.3.3

[PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Aleksey Makarov]

From: David Daney <david.daney@cavium.com>

Needed for little-endian ioport access.
This fixes NOR flash in little-endian mode

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
---
 .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 ++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/mangle-port.h

diff --git a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
new file mode 100644
index 0000000..374eefa
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#include <asm/byteorder.h>
+
+#ifdef __BIG_ENDIAN
+
+# define __swizzle_addr_b(port)	(port)
+# define __swizzle_addr_w(port)	(port)
+# define __swizzle_addr_l(port)	(port)
+# define __swizzle_addr_q(port)	(port)
+
+#else /* __LITTLE_ENDIAN */
+
+static inline bool __should_swizzle_addr(unsigned long p)
+{
+	/* boot bus? */
+	return ((p >> 40) & 0xff) == 0;
+}
+
+# define __swizzle_addr_b(port)	\
+	(__should_swizzle_addr(port) ? (port) ^ 7 : (port))
+# define __swizzle_addr_w(port)	\
+	(__should_swizzle_addr(port) ? (port) ^ 6 : (port))
+# define __swizzle_addr_l(port)	\
+	(__should_swizzle_addr(port) ? (port) ^ 4 : (port))
+# define __swizzle_addr_q(port)	(port)
+
+#endif /* __BIG_ENDIAN */
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		le16_to_cpu(x)
+# define __mem_ioswabw(a, x)	(x)
+# define ioswabl(a, x)		le32_to_cpu(x)
+# define __mem_ioswabl(a, x)	(x)
+# define ioswabq(a, x)		le64_to_cpu(x)
+# define __mem_ioswabq(a, x)	(x)
+
+#else
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		(x)
+# define __mem_ioswabw(a, x)	cpu_to_le16(x)
+# define ioswabl(a, x)		(x)
+# define __mem_ioswabl(a, x)	cpu_to_le32(x)
+# define ioswabq(a, x)		(x)
+# define __mem_ioswabq(a, x)	cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
-- 
2.3.3

[PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Aleksey Makarov]

From: David Daney <david.daney@cavium.com>

Needed for little-endian ioport access.
This fixes NOR flash in little-endian mode

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
---
 .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 ++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/mangle-port.h

diff --git a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
new file mode 100644
index 0000000..374eefa
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#include <asm/byteorder.h>
+
+#ifdef __BIG_ENDIAN
+
+# define __swizzle_addr_b(port)	(port)
+# define __swizzle_addr_w(port)	(port)
+# define __swizzle_addr_l(port)	(port)
+# define __swizzle_addr_q(port)	(port)
+
+#else /* __LITTLE_ENDIAN */
+
+static inline bool __should_swizzle_addr(unsigned long p)
+{
+	/* boot bus? */
+	return ((p >> 40) & 0xff) == 0;
+}
+
+# define __swizzle_addr_b(port)	\
+	(__should_swizzle_addr(port) ? (port) ^ 7 : (port))
+# define __swizzle_addr_w(port)	\
+	(__should_swizzle_addr(port) ? (port) ^ 6 : (port))
+# define __swizzle_addr_l(port)	\
+	(__should_swizzle_addr(port) ? (port) ^ 4 : (port))
+# define __swizzle_addr_q(port)	(port)
+
+#endif /* __BIG_ENDIAN */
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		le16_to_cpu(x)
+# define __mem_ioswabw(a, x)	(x)
+# define ioswabl(a, x)		le32_to_cpu(x)
+# define __mem_ioswabl(a, x)	(x)
+# define ioswabq(a, x)		le64_to_cpu(x)
+# define __mem_ioswabq(a, x)	(x)
+
+#else
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		(x)
+# define __mem_ioswabw(a, x)	cpu_to_le16(x)
+# define ioswabl(a, x)		(x)
+# define __mem_ioswabl(a, x)	cpu_to_le32(x)
+# define ioswabq(a, x)		(x)
+# define __mem_ioswabq(a, x)	cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
-- 
2.3.3

[PATCH 3/3] MIPS: OCTEON: Enable little endian kernel.

[Aleksey Makarov]

From: David Daney <david.daney@cavium.com>

Now it is supported, so let people select it.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
---
 arch/mips/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3086b87..a6ca5e1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -779,7 +779,8 @@ config CAVIUM_OCTEON_SOC
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select EDAC_SUPPORT
-	select SYS_SUPPORTS_HOTPLUG_CPU
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HOTPLUG_CPU if CONFIG_CPU_BIG_ENDIAN
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_HAS_CPU_CAVIUM_OCTEON
 	select SWAP_IO_SPACE
-- 
2.3.3

[PATCH 3/3] MIPS: OCTEON: Enable little endian kernel.

[Aleksey Makarov]

From: David Daney <david.daney@cavium.com>

Now it is supported, so let people select it.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
---
 arch/mips/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3086b87..a6ca5e1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -779,7 +779,8 @@ config CAVIUM_OCTEON_SOC
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select EDAC_SUPPORT
-	select SYS_SUPPORTS_HOTPLUG_CPU
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HOTPLUG_CPU if CONFIG_CPU_BIG_ENDIAN
 	select SYS_HAS_EARLY_PRINTK
 	select SYS_HAS_CPU_CAVIUM_OCTEON
 	select SWAP_IO_SPACE
-- 
2.3.3

Re: [PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Paul Martin]

On Fri, Mar 20, 2015 at 07:11:57PM +0300, Aleksey Makarov wrote:
> From: David Daney <david.daney@cavium.com>
> 
> Needed for little-endian ioport access.
> This fixes NOR flash in little-endian mode
> 
> Signed-off-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
> ---
>  .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 ++++++++++++++++++++++

This seems to be a new header file that's not used anywhere else.

I get the feeling that there should be at least another three patches
in this series which have been omitted.

Certainly, the Octeon peripherals won't work with just the three part
patch set presented here.

Thanks for this patch (and the padding bugfix to the boot structure).

PS. Don't forget the missing htons() in drivers/staging/octeon/ethernet-tx.c

-- 
Paul Martin                                  http://www.codethink.co.uk/
Senior Software Developer, Codethink Ltd.

Re: [PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Aleksey Makarov]

> On Fri, Mar 20, 2015 at 07:11:57PM +0300, Aleksey Makarov wrote:
>> From: David Daney <david.daney@cavium.com>
>> 
>> Needed for little-endian ioport access.
>> This fixes NOR flash in little-endian mode
>> 
>> Signed-off-by: David Daney <david.daney@cavium.com>
>> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
>> ---
>>  .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 
>> ++++++++++++++++++++++
> 
> This seems to be a new header file that's not used anywhere else.

arch/mips/include/asm/io.h:#include <mangle-port.h>

Also note the compiler flags:

-I./arch/mips/include/asm/mach-cavium-octeon -I./arch/mips/include/asm/mach-generic 

> I get the feeling that there should be at least another three patches
> in this series which have been omitted.
> 
> Certainly, the Octeon peripherals won't work with just the three part
> patch set presented here.

With these patches the cn7000 board boots in little-endian mode with 
all peripherials supported on this board working fine.  The peripherials
on other boards should probably be fixed separately.

> PS. Don't forget the missing htons() in drivers/staging/octeon/ethernet-tx.c

Thanks.  A patch would be appreciated.

Thanks
Aleksey Makarov

Re: [PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Aleksey Makarov]

> On Fri, Mar 20, 2015 at 07:11:57PM +0300, Aleksey Makarov wrote:
>> From: David Daney <david.daney@cavium.com>
>> 
>> Needed for little-endian ioport access.
>> This fixes NOR flash in little-endian mode
>> 
>> Signed-off-by: David Daney <david.daney@cavium.com>
>> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
>> ---
>>  .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 
>> ++++++++++++++++++++++
> 
> This seems to be a new header file that's not used anywhere else.

arch/mips/include/asm/io.h:#include <mangle-port.h>

Also note the compiler flags:

-I./arch/mips/include/asm/mach-cavium-octeon -I./arch/mips/include/asm/mach-generic 

> I get the feeling that there should be at least another three patches
> in this series which have been omitted.
> 
> Certainly, the Octeon peripherals won't work with just the three part
> patch set presented here.

With these patches the cn7000 board boots in little-endian mode with 
all peripherials supported on this board working fine.  The peripherials
on other boards should probably be fixed separately.

> PS. Don't forget the missing htons() in drivers/staging/octeon/ethernet-tx.c

Thanks.  A patch would be appreciated.

Thanks
Aleksey Makarov

Re: [PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Aleksey Makarov]

> On Fri, Mar 20, 2015 at 07:11:57PM +0300, Aleksey Makarov wrote:
>> From: David Daney <david.daney@cavium.com>
>> 
>> Needed for little-endian ioport access.
>> This fixes NOR flash in little-endian mode
>> 
>> Signed-off-by: David Daney <david.daney@cavium.com>
>> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
>> ---
>>  .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 
>> ++++++++++++++++++++++
> 
> This seems to be a new header file that's not used anywhere else.

arch/mips/include/asm/io.h:#include <mangle-port.h>

Also note the compiler flags:

-I./arch/mips/include/asm/mach-cavium-octeon -I./arch/mips/include/asm/mach-generic 

> I get the feeling that there should be at least another three patches
> in this series which have been omitted.
> 
> Certainly, the Octeon peripherals won't work with just the three part
> patch set presented here.

With these patches the cn7000 board boots in little-endian mode with 
all peripherials supported on this board working fine.  The peripherials
on other boards should probably be fixed separately.

> PS. Don't forget the missing htons() in drivers/staging/octeon/ethernet-tx.c

Thanks.  A patch would be appreciated.

Thanks
Aleksey Makarov

Re: [PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Aleksey Makarov]

> On Fri, Mar 20, 2015 at 07:11:57PM +0300, Aleksey Makarov wrote:
>> From: David Daney <david.daney@cavium.com>
>> 
>> Needed for little-endian ioport access.
>> This fixes NOR flash in little-endian mode
>> 
>> Signed-off-by: David Daney <david.daney@cavium.com>
>> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
>> ---
>>  .../include/asm/mach-cavium-octeon/mangle-port.h   | 74 
>> ++++++++++++++++++++++
> 
> This seems to be a new header file that's not used anywhere else.

arch/mips/include/asm/io.h:#include <mangle-port.h>

Also note the compiler flags:

-I./arch/mips/include/asm/mach-cavium-octeon -I./arch/mips/include/asm/mach-generic 

> I get the feeling that there should be at least another three patches
> in this series which have been omitted.
> 
> Certainly, the Octeon peripherals won't work with just the three part
> patch set presented here.

With these patches the cn7000 board boots in little-endian mode with 
all peripherials supported on this board working fine.  The peripherials
on other boards should probably be fixed separately.

> PS. Don't forget the missing htons() in drivers/staging/octeon/ethernet-tx.c

Thanks.  A patch would be appreciated.

Thanks
Aleksey Makarov

Re: [PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[Paul Martin]

On Mon, Mar 23, 2015 at 05:04:08PM +0300, Aleksey Makarov wrote:

> With these patches the cn7000 board boots in little-endian mode with 
> all peripherials supported on this board working fine.  The peripherials
> on other boards should probably be fixed separately.

Including octeon-rng?  :-)

-- 
Paul Martin                                  http://www.codethink.co.uk/
Senior Software Developer, Codethink Ltd.

Re: [PATCH 2/3] MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

[David Daney]

On 03/23/2015 07:18 AM, Paul Martin wrote:
> On Mon, Mar 23, 2015 at 05:04:08PM +0300, Aleksey Makarov wrote:
>
>> With these patches the cn7000 board boots in little-endian mode with
>> all peripherials supported on this board working fine.  The peripherials
>> on other boards should probably be fixed separately.
>
> Including octeon-rng?  :-)

It should, I don't think there is any endian dependent code in there.

Most OCTEON drivers that don't do DMA should not have any hardware 
endian dependencies.

Things like I2C, MDIO, and SPI shouldn't need any changes.

David Daney