From: <Claudiu.Beznea@microchip.com>
To: <peda@axentia.se>, <linux-kernel@vger.kernel.org>
Cc: alexandre.belloni@bootlin.com, clement.leger@bootlin.com,
linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: at91: fix build for SAMA5D3 w/o L2 cache
Date: Thu, 24 Nov 2022 10:52:18 +0000 [thread overview]
Message-ID: <55153e71-9b2d-c0ba-a36f-685dafb2743a@microchip.com> (raw)
In-Reply-To: <b7f8dacc-5e1f-0eb2-188e-3ad9a9f7613d@axentia.se>
On 12.11.2022 17:40, Peter Rosin wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The L2 cache is present on the newer SAMA5D2 and SAMA5D4 families, but
> apparently not for the older SAMA5D3. At least not always.
>
> Solves a build-time regression with the following symptom:
>
> sama5.c:(.init.text+0x48): undefined reference to `outer_cache'
>
> Fixes: 3b5a7ca7d252 ("ARM: at91: setup outer cache .write_sec() callback if needed")
> Signed-off-by: Peter Rosin <peda@axentia.se>
Applied to at91-fixes, thanks!
> ---
> arch/arm/mach-at91/sama5.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Hi!
>
> I'm not sure this is the correct solution? Maybe SAMA5D3 should bring
> in CONFIG_OUTER_CACHE unconditionally instead? But that seems like a
> bigger change, and not just a tweak of the regressing commit...
>
> Cheers,
> Peter
>
> diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
> index 67ed68fbe3a5..bf2b5c6a18c6 100644
> --- a/arch/arm/mach-at91/sama5.c
> +++ b/arch/arm/mach-at91/sama5.c
> @@ -26,7 +26,7 @@ static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
> static void __init sama5_secure_cache_init(void)
> {
> sam_secure_init();
> - if (sam_linux_is_optee_available())
> + if (IS_ENABLED(CONFIG_OUTER_CACHE) && sam_linux_is_optee_available())
> outer_cache.write_sec = sama5_l2c310_write_sec;
> }
>
> --
> 2.20.1
>
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WARNING: multiple messages have this Message-ID (diff)
From: <Claudiu.Beznea@microchip.com>
To: <peda@axentia.se>, <linux-kernel@vger.kernel.org>
Cc: <linux@armlinux.org.uk>, <Nicolas.Ferre@microchip.com>,
<alexandre.belloni@bootlin.com>, <clement.leger@bootlin.com>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] ARM: at91: fix build for SAMA5D3 w/o L2 cache
Date: Thu, 24 Nov 2022 10:52:18 +0000 [thread overview]
Message-ID: <55153e71-9b2d-c0ba-a36f-685dafb2743a@microchip.com> (raw)
In-Reply-To: <b7f8dacc-5e1f-0eb2-188e-3ad9a9f7613d@axentia.se>
On 12.11.2022 17:40, Peter Rosin wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The L2 cache is present on the newer SAMA5D2 and SAMA5D4 families, but
> apparently not for the older SAMA5D3. At least not always.
>
> Solves a build-time regression with the following symptom:
>
> sama5.c:(.init.text+0x48): undefined reference to `outer_cache'
>
> Fixes: 3b5a7ca7d252 ("ARM: at91: setup outer cache .write_sec() callback if needed")
> Signed-off-by: Peter Rosin <peda@axentia.se>
Applied to at91-fixes, thanks!
> ---
> arch/arm/mach-at91/sama5.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Hi!
>
> I'm not sure this is the correct solution? Maybe SAMA5D3 should bring
> in CONFIG_OUTER_CACHE unconditionally instead? But that seems like a
> bigger change, and not just a tweak of the regressing commit...
>
> Cheers,
> Peter
>
> diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
> index 67ed68fbe3a5..bf2b5c6a18c6 100644
> --- a/arch/arm/mach-at91/sama5.c
> +++ b/arch/arm/mach-at91/sama5.c
> @@ -26,7 +26,7 @@ static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
> static void __init sama5_secure_cache_init(void)
> {
> sam_secure_init();
> - if (sam_linux_is_optee_available())
> + if (IS_ENABLED(CONFIG_OUTER_CACHE) && sam_linux_is_optee_available())
> outer_cache.write_sec = sama5_l2c310_write_sec;
> }
>
> --
> 2.20.1
>
next prev parent reply other threads:[~2022-11-24 10:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-12 15:40 [PATCH] ARM: at91: fix build for SAMA5D3 w/o L2 cache Peter Rosin
2022-11-12 15:40 ` Peter Rosin
2022-11-18 21:38 ` Peter Rosin
2022-11-18 21:38 ` Peter Rosin
2022-11-22 15:13 ` Thorsten Leemhuis
2022-11-22 15:13 ` Thorsten Leemhuis
2022-11-22 17:14 ` Clément Léger
2022-11-22 17:14 ` Clément Léger
2022-11-23 7:19 ` Claudiu.Beznea
2022-11-23 7:19 ` Claudiu.Beznea
2022-11-23 8:38 ` Peter Rosin
2022-11-23 8:38 ` Peter Rosin
2022-11-23 10:40 ` Nicolas Ferre
2022-11-23 10:40 ` Nicolas Ferre
2022-11-24 10:52 ` Claudiu.Beznea [this message]
2022-11-24 10:52 ` Claudiu.Beznea
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