From: Julien Grall <julien.grall@linaro.org>
To: Ian Campbell <ian.campbell@citrix.com>, xen-devel@lists.xen.org
Cc: tim@xen.org, stefano.stabellini@eu.citrix.com
Subject: Re: [PATCH v4 08/15] xen: arm: don't pretend to handle cache maintenance by set/way
Date: Fri, 27 Mar 2015 16:36:28 +0000 [thread overview]
Message-ID: <5515870C.1080702@linaro.org> (raw)
In-Reply-To: <1427466824-31967-8-git-send-email-ian.campbell@citrix.com>
Hi Ian,
On 27/03/15 14:33, Ian Campbell wrote:
> We set HCR_EL2.TSW but only (sort of) handle 32-bit access to DCCISW
> but not the other two registers, nor any 64-bit access. Add handlers
> for all of these.
We don't set HCR_EL2.TSW so DCCISW is not trapped.
> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
> index c2dcb66..cf3d6cc 100644
> --- a/xen/include/public/arch-arm.h
> +++ b/xen/include/public/arch-arm.h
> @@ -161,6 +161,11 @@
> *
> * - The device tree Xen compatible node is fully described under Linux
> * at Documentation/devicetree/bindings/arm/xen.txt.
> + *
> + * - Cache maintenaince operations by set/way ("dc isw|cisw|csw" and
> + * the equivalent cp15 registers) are not available when running
> + * under Xen and will result in an undefined instruction exception
> + * delivered to the guest.
> */
set/way operations is used by Linux ARM32 in order to flush all the
cache. Injecting an undefined instruction would make guest unusable.
Regards,
--
Julien Grall
next prev parent reply other threads:[~2015-03-27 16:36 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-27 14:33 [PATCH v4 0/15] xen: arm: reenable support for 32-bit userspace running in 64-bit guest Ian Campbell
2015-03-27 14:33 ` [PATCH v4 01/15] xen: arm: Correct PMXEV cp register definitions Ian Campbell
2015-03-27 14:33 ` [PATCH v4 02/15] xen: arm: Factor out psr_mode_is_user Ian Campbell
2015-03-27 14:33 ` [PATCH v4 03/15] xen: arm: correctly handle vtimer traps from userspace Ian Campbell
2015-03-27 15:57 ` Julien Grall
2015-03-27 14:33 ` [PATCH v4 04/15] xen: arm: handle accesses to CNTP_CVAL_EL0 Ian Campbell
2015-03-27 15:58 ` Julien Grall
2015-03-27 14:33 ` [PATCH v4 05/15] xen: arm: Use ARMv8 names for CNTHCTL_EL2 bits Ian Campbell
2015-03-27 14:33 ` [PATCH v4 06/15] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap Ian Campbell
2015-03-27 14:33 ` [PATCH v4 07/15] xen: arm: do not handle traps accessing CLIDR_EL1 or CCSIDR_EL1 Ian Campbell
2015-03-27 16:09 ` Julien Grall
2015-03-27 14:33 ` [PATCH v4 08/15] xen: arm: don't pretend to handle cache maintenance by set/way Ian Campbell
2015-03-27 16:36 ` Julien Grall [this message]
2015-03-27 17:05 ` Ian Campbell
2015-03-30 12:17 ` Julien Grall
2015-03-30 13:30 ` Ian Campbell
2015-03-30 13:45 ` Processed: " xen
2015-03-27 14:33 ` [PATCH v4 09/15] xen: arm: Handle CP15 register traps from userspace Ian Campbell
2015-03-27 16:39 ` Julien Grall
2015-03-27 14:33 ` [PATCH v4 10/15] xen: arm: Handle CP14 32-bit register accesses " Ian Campbell
2015-03-27 14:33 ` [PATCH v4 11/15] xen: arm: correctly handle sysreg " Ian Campbell
2015-03-27 16:40 ` Julien Grall
2015-03-27 14:33 ` [PATCH v4 12/15] xen: arm: handle remaining traps " Ian Campbell
2015-03-27 14:33 ` [PATCH v4 13/15] xen: arm: Dump guest state when invalid trap state is detected Ian Campbell
2015-03-27 14:33 ` [PATCH v4 14/15] xen: arm: Allow traps from 32 bit userspace on 64 bit hypervisors again Ian Campbell
2015-03-27 14:33 ` [PATCH v4 15/15] xen: arm: always omit guest user stack in vcpu_show_execution_state Ian Campbell
2015-03-27 16:42 ` Julien Grall
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