From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
"Michael S. Tsirkin" <mst@redhat.com>
Cc: xen-devel@lists.xensource.com, pmatouse@redhat.com,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Xen-devel] [PATCH][XSA-126] xen: limit guest control of PCI command register
Date: Wed, 1 Apr 2015 10:41:12 +0100 [thread overview]
Message-ID: <551BBD38.60204@citrix.com> (raw)
In-Reply-To: <alpine.DEB.2.02.1504011012030.7690@kaball.uk.xensource.com>
On 01/04/15 10:20, Stefano Stabellini wrote:
> CC'ing the author of the patch and xen-devel.
> FYI I think that Jan is going to be on vacation for a couple of weeks.
>
> On Wed, 1 Apr 2015, Michael S. Tsirkin wrote:
>> On Tue, Mar 31, 2015 at 03:18:03PM +0100, Stefano Stabellini wrote:
>>> From: Jan Beulich <jbeulich@suse.com>
>>>
>>> Otherwise the guest can abuse that control to cause e.g. PCIe
>>> Unsupported Request responses (by disabling memory and/or I/O decoding
>>> and subsequently causing [CPU side] accesses to the respective address
>>> ranges), which (depending on system configuration) may be fatal to the
>>> host.
>>>
>>> This is CVE-2015-2756 / XSA-126.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
>>> Acked-by: Ian Campbell <ian.campbell@citrix.com>
>> The patch description seems somewhat incorrect to me.
>> UR should not be fatal to the system, and it's not platform
>> specific.
> I think that people have been able to repro this, but I'll let Jan
> comment on it.
Depending on how the BIOS sets up AER (if even available), a UR can very
easily be fatal to the system.
If firmware first mode is set, Xen (or indeed Linux) can't fix a
problematic setup. Experimentally, doing so can cause infinite loops in
certain vendors SMM handlers.
>
>
>> In particular, there could be more reasons for devices
>> to generate URs, for example, if they get a transaction
>> during FLR. I don't think we ever tried to prevent this.
> That cannot be triggered by guest behaviour.
What cannot be triggered by guest behaviour?
Many devices have secondary access into config space via a BAR, which
allows a guest driver full and unmediated control of everything.
Under Xen, we have covered this with XSA-124 which basically says that
for such devices, all bets are off.
~Andrew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
"Michael S. Tsirkin" <mst@redhat.com>
Cc: xen-devel@lists.xensource.com, pmatouse@redhat.com,
qemu-devel@nongnu.org
Subject: Re: [Xen-devel] [PATCH][XSA-126] xen: limit guest control of PCI command register
Date: Wed, 1 Apr 2015 10:41:12 +0100 [thread overview]
Message-ID: <551BBD38.60204@citrix.com> (raw)
In-Reply-To: <alpine.DEB.2.02.1504011012030.7690@kaball.uk.xensource.com>
On 01/04/15 10:20, Stefano Stabellini wrote:
> CC'ing the author of the patch and xen-devel.
> FYI I think that Jan is going to be on vacation for a couple of weeks.
>
> On Wed, 1 Apr 2015, Michael S. Tsirkin wrote:
>> On Tue, Mar 31, 2015 at 03:18:03PM +0100, Stefano Stabellini wrote:
>>> From: Jan Beulich <jbeulich@suse.com>
>>>
>>> Otherwise the guest can abuse that control to cause e.g. PCIe
>>> Unsupported Request responses (by disabling memory and/or I/O decoding
>>> and subsequently causing [CPU side] accesses to the respective address
>>> ranges), which (depending on system configuration) may be fatal to the
>>> host.
>>>
>>> This is CVE-2015-2756 / XSA-126.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
>>> Acked-by: Ian Campbell <ian.campbell@citrix.com>
>> The patch description seems somewhat incorrect to me.
>> UR should not be fatal to the system, and it's not platform
>> specific.
> I think that people have been able to repro this, but I'll let Jan
> comment on it.
Depending on how the BIOS sets up AER (if even available), a UR can very
easily be fatal to the system.
If firmware first mode is set, Xen (or indeed Linux) can't fix a
problematic setup. Experimentally, doing so can cause infinite loops in
certain vendors SMM handlers.
>
>
>> In particular, there could be more reasons for devices
>> to generate URs, for example, if they get a transaction
>> during FLR. I don't think we ever tried to prevent this.
> That cannot be triggered by guest behaviour.
What cannot be triggered by guest behaviour?
Many devices have secondary access into config space via a BAR, which
allows a guest driver full and unmediated control of everything.
Under Xen, we have covered this with XSA-124 which basically says that
for such devices, all bets are off.
~Andrew
next prev parent reply other threads:[~2015-04-01 9:47 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-31 14:18 [Qemu-devel] [PATCH][XSA-126] xen: limit guest control of PCI command register Stefano Stabellini
2015-04-01 9:01 ` Michael S. Tsirkin
2015-04-01 9:20 ` Stefano Stabellini
2015-04-01 9:20 ` Stefano Stabellini
2015-04-01 9:32 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-01 9:32 ` Michael S. Tsirkin
2015-04-01 9:41 ` Andrew Cooper [this message]
2015-04-01 9:41 ` [Xen-devel] " Andrew Cooper
2015-04-01 9:59 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-01 9:59 ` Michael S. Tsirkin
2015-04-13 8:17 ` [Qemu-devel] " Jan Beulich
2015-04-13 8:17 ` Jan Beulich
2015-04-13 11:19 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-13 11:19 ` Michael S. Tsirkin
2015-04-13 11:34 ` [Qemu-devel] " Jan Beulich
2015-04-13 11:34 ` Jan Beulich
2015-04-13 11:47 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-13 11:47 ` Michael S. Tsirkin
2015-04-13 12:40 ` [Qemu-devel] " Jan Beulich
2015-04-13 12:40 ` Jan Beulich
2015-04-13 12:47 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-13 12:47 ` Michael S. Tsirkin
2015-04-13 12:51 ` [Qemu-devel] " Jan Beulich
2015-04-13 12:51 ` Jan Beulich
2015-04-20 13:43 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-20 13:43 ` Michael S. Tsirkin
2015-04-20 14:08 ` [Qemu-devel] " Jan Beulich
2015-04-20 14:08 ` Jan Beulich
2015-04-20 14:32 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-20 14:32 ` Michael S. Tsirkin
2015-04-20 14:57 ` [Qemu-devel] " Jan Beulich
2015-04-20 14:57 ` Jan Beulich
2015-06-07 6:23 ` [Qemu-devel] " Michael S. Tsirkin
2015-06-07 6:23 ` Michael S. Tsirkin
2015-06-08 7:42 ` [Qemu-devel] " Jan Beulich
2015-06-08 7:42 ` Jan Beulich
2015-06-08 8:09 ` [Qemu-devel] " Malcolm Crossley
2015-06-08 8:09 ` Malcolm Crossley
2015-06-08 8:59 ` [Qemu-devel] [Xen-devel] " Michael S. Tsirkin
2015-06-08 8:59 ` Michael S. Tsirkin
2015-06-08 9:03 ` [Qemu-devel] " Jan Beulich
2015-06-08 9:03 ` Jan Beulich
2015-06-08 9:36 ` [Qemu-devel] " Michael S. Tsirkin
2015-06-08 9:36 ` Michael S. Tsirkin
2015-06-08 10:55 ` [Qemu-devel] " Jan Beulich
2015-06-08 10:55 ` Jan Beulich
2015-06-08 11:28 ` [Qemu-devel] " Michael S. Tsirkin
2015-06-08 11:28 ` Michael S. Tsirkin
2015-06-08 11:44 ` [Qemu-devel] " Jan Beulich
2015-06-08 11:44 ` Jan Beulich
2015-06-10 7:00 ` [Qemu-devel] " Jan Beulich
2015-06-10 7:00 ` Jan Beulich
2015-06-10 11:43 ` [Qemu-devel] " Michael S. Tsirkin
2015-06-10 11:43 ` Michael S. Tsirkin
2015-06-10 12:06 ` [Qemu-devel] " Jan Beulich
2015-06-10 12:06 ` Jan Beulich
2015-06-10 13:35 ` [Qemu-devel] [Xen-devel] " Michael S. Tsirkin
2015-06-10 13:35 ` Michael S. Tsirkin
2015-06-08 9:30 ` [Qemu-devel] " Michael S. Tsirkin
2015-06-08 9:30 ` Michael S. Tsirkin
2015-06-08 10:38 ` [Qemu-devel] " Jan Beulich
2015-06-08 10:38 ` Jan Beulich
2015-06-10 7:08 ` [Qemu-devel] " Jan Beulich
2015-06-10 7:08 ` Jan Beulich
2015-06-10 11:46 ` [Qemu-devel] " Michael S. Tsirkin
2015-06-10 11:46 ` Michael S. Tsirkin
2015-06-10 12:10 ` [Qemu-devel] " Jan Beulich
2015-06-10 12:10 ` Jan Beulich
2015-04-01 9:50 ` [Qemu-devel] " Ian Campbell
2015-04-01 9:50 ` Ian Campbell
2015-04-01 10:12 ` [Qemu-devel] " Michael S. Tsirkin
2015-04-01 10:12 ` Michael S. Tsirkin
2015-04-09 18:10 ` [Qemu-devel] " Peter Maydell
2015-04-10 11:45 ` Peter Maydell
2015-04-10 11:49 ` Peter Maydell
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