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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Chao Peng <chao.p.peng@linux.intel.com>, xen-devel@lists.xen.org
Cc: keir@xen.org, Ian.Campbell@citrix.com,
	stefano.stabellini@eu.citrix.com, Ian.Jackson@eu.citrix.com,
	will.auld@intel.com, JBeulich@suse.com, wei.liu2@citrix.com,
	dgdegra@tycho.nsa.gov
Subject: Re: [PATCH v4 02/12] x86: improve psr scheduling code
Date: Thu, 09 Apr 2015 22:01:53 +0100	[thread overview]
Message-ID: <5526E8C1.3060302@citrix.com> (raw)
In-Reply-To: <1428571105-3604-3-git-send-email-chao.p.peng@linux.intel.com>

On 09/04/2015 10:18, Chao Peng wrote:
> Switching RMID from previous vcpu to next vcpu only needs to write
> MSR_IA32_PSR_ASSOC once. Write it with the value of next vcpu is enough,
> no need to write '0' first. Idle domain has RMID set to 0 and because MSR
> is already updated lazily, so just switch it as it does.
>
> Also move the initialization of per-CPU variable which used for lazy
> update from context switch to CPU starting.
>
> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> ---
> Changes in v4:
> * Move psr_assoc_reg_read/psr_assoc_reg_write into psr_ctxt_switch_to.
> * Use 0 instead of smp_processor_id() for boot cpu.
> * add cpu parameter to psr_assoc_init.
> Changes in v2:
> * Move initialization for psr_assoc from context switch to CPU_STARTING.
> ---
>  xen/arch/x86/domain.c     |  7 ++---
>  xen/arch/x86/psr.c        | 75 ++++++++++++++++++++++++++++++++++-------------
>  xen/include/asm-x86/psr.h |  3 +-
>  3 files changed, 59 insertions(+), 26 deletions(-)
>
> diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
> index 04c1898..695a2eb 100644
> --- a/xen/arch/x86/domain.c
> +++ b/xen/arch/x86/domain.c
> @@ -1444,8 +1444,6 @@ static void __context_switch(void)
>      {
>          memcpy(&p->arch.user_regs, stack_regs, CTXT_SWITCH_STACK_BYTES);
>          vcpu_save_fpu(p);
> -        if ( psr_cmt_enabled() )
> -            psr_assoc_rmid(0);
>          p->arch.ctxt_switch_from(p);
>      }
>  
> @@ -1470,11 +1468,10 @@ static void __context_switch(void)
>          }
>          vcpu_restore_fpu_eager(n);
>          n->arch.ctxt_switch_to(n);
> -
> -        if ( psr_cmt_enabled() && n->domain->arch.psr_rmid > 0 )
> -            psr_assoc_rmid(n->domain->arch.psr_rmid);
>      }
>  
> +    psr_ctxt_switch_to(n->domain);
> +
>      gdt = !is_pv_32on64_vcpu(n) ? per_cpu(gdt_table, cpu) :
>                                    per_cpu(compat_gdt_table, cpu);
>      if ( need_full_gdt(n) )
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index 344de3c..6119c6e 100644
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -22,7 +22,6 @@
>  
>  struct psr_assoc {
>      uint64_t val;
> -    bool_t initialized;
>  };
>  
>  struct psr_cmt *__read_mostly psr_cmt;
> @@ -122,14 +121,6 @@ static void __init init_psr_cmt(unsigned int rmid_max)
>      printk(XENLOG_INFO "Cache Monitoring Technology enabled\n");
>  }
>  
> -static int __init init_psr(void)
> -{
> -    if ( (opt_psr & PSR_CMT) && opt_rmid_max )
> -        init_psr_cmt(opt_rmid_max);
> -    return 0;
> -}
> -__initcall(init_psr);
> -
>  /* Called with domain lock held, no psr specific lock needed */
>  int psr_alloc_rmid(struct domain *d)
>  {
> @@ -175,26 +166,70 @@ void psr_free_rmid(struct domain *d)
>      d->arch.psr_rmid = 0;
>  }
>  
> -void psr_assoc_rmid(unsigned int rmid)
> +static inline void psr_assoc_init(unsigned int cpu)
> +{
> +    struct psr_assoc *psra = &per_cpu(psr_assoc, cpu);
> +
> +    if ( psr_cmt_enabled() )
> +        rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
> +}

On further consideration, this would probably be better as a void
function which used this_cpu() rather than per_cpu().

Absolutely nothing good can come of calling it with cpu !=
smp_processor_id(), so we should avoid that situation arising in the
first place.

> +
> +static inline void psr_assoc_rmid(uint64_t *reg, unsigned int rmid)
> +{
> +    *reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
> +}
> +
> +void psr_ctxt_switch_to(struct domain *d)
>  {
> -    uint64_t val;
> -    uint64_t new_val;
>      struct psr_assoc *psra = &this_cpu(psr_assoc);
> +    uint64_t reg = psra->val;
> +
> +    if ( psr_cmt_enabled() )
> +        psr_assoc_rmid(&reg, d->arch.psr_rmid);
>  
> -    if ( !psra->initialized )
> +    if ( reg != psra->val )
>      {
> -        rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
> -        psra->initialized = 1;
> +        wrmsrl(MSR_IA32_PSR_ASSOC, reg);
> +        psra->val = reg;
>      }
> -    val = psra->val;
> +}
>  
> -    new_val = (val & ~rmid_mask) | (rmid & rmid_mask);
> -    if ( val != new_val )
> +static void psr_cpu_init(unsigned int cpu)
> +{
> +    psr_assoc_init(cpu);
> +}

This can also turn into a void helper.

Otherwise, Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

~Andrew

> +
> +static int cpu_callback(
> +    struct notifier_block *nfb, unsigned long action, void *hcpu)
> +{
> +    unsigned int cpu = (unsigned long)hcpu;
> +
> +    switch ( action )
>      {
> -        wrmsrl(MSR_IA32_PSR_ASSOC, new_val);
> -        psra->val = new_val;
> +    case CPU_STARTING:
> +        psr_cpu_init(cpu);
> +        break;
>      }
> +
> +    return NOTIFY_DONE;
> +}
> +
> +static struct notifier_block cpu_nfb = {
> +    .notifier_call = cpu_callback
> +};
> +
> +static int __init psr_presmp_init(void)
> +{
> +    if ( (opt_psr & PSR_CMT) && opt_rmid_max )
> +        init_psr_cmt(opt_rmid_max);
> +
> +    psr_cpu_init(0);
> +    if ( psr_cmt_enabled() )
> +        register_cpu_notifier(&cpu_nfb);
> +
> +    return 0;
>  }
> +presmp_initcall(psr_presmp_init);
>  
>  /*
>   * Local variables:
> diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
> index c6076e9..585350c 100644
> --- a/xen/include/asm-x86/psr.h
> +++ b/xen/include/asm-x86/psr.h
> @@ -46,7 +46,8 @@ static inline bool_t psr_cmt_enabled(void)
>  
>  int psr_alloc_rmid(struct domain *d);
>  void psr_free_rmid(struct domain *d);
> -void psr_assoc_rmid(unsigned int rmid);
> +
> +void psr_ctxt_switch_to(struct domain *d);
>  
>  #endif /* __ASM_PSR_H__ */
>  

  reply	other threads:[~2015-04-09 21:01 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-09  9:18 [PATCH v4 00/12] enable Cache Allocation Technology (CAT) for VMs Chao Peng
2015-04-09  9:18 ` [PATCH v4 01/12] x86: clean up psr boot parameter parsing Chao Peng
2015-04-09 20:38   ` Andrew Cooper
2015-04-09  9:18 ` [PATCH v4 02/12] x86: improve psr scheduling code Chao Peng
2015-04-09 21:01   ` Andrew Cooper [this message]
2015-04-10  7:24     ` Chao Peng
2015-04-10  9:28       ` Andrew Cooper
2015-04-09  9:18 ` [PATCH v4 03/12] x86: detect and initialize Intel CAT feature Chao Peng
2015-04-09 21:30   ` Andrew Cooper
2015-04-09  9:18 ` [PATCH v4 04/12] x86: maintain COS to CBM mapping for each socket Chao Peng
2015-04-09 21:35   ` Andrew Cooper
2015-04-10  7:26     ` Chao Peng
2015-04-09  9:18 ` [PATCH v4 05/12] x86: maintain socket CPU mask for CAT Chao Peng
2015-04-09 21:45   ` Andrew Cooper
2015-04-10  7:33     ` Chao Peng
2015-04-10  9:48       ` Andrew Cooper
2015-04-09  9:18 ` [PATCH v4 06/12] x86: add COS information for each domain Chao Peng
2015-04-09 21:54   ` Andrew Cooper
2015-04-10  7:35     ` Chao Peng
2015-04-09  9:18 ` [PATCH v4 07/12] x86: expose CBM length and COS number information Chao Peng
2015-04-09 21:54   ` Andrew Cooper
2015-04-09  9:18 ` [PATCH v4 08/12] x86: dynamically get/set CBM for a domain Chao Peng
2015-04-09 22:06   ` Andrew Cooper
2015-04-10  7:37     ` Chao Peng
2015-04-09  9:18 ` [PATCH v4 09/12] x86: add scheduling support for Intel CAT Chao Peng
2015-04-09 22:12   ` Andrew Cooper
2015-04-10  7:41     ` Chao Peng
2015-04-09  9:18 ` [PATCH v4 10/12] xsm: add CAT related xsm policies Chao Peng
2015-04-09  9:18 ` [PATCH v4 11/12] tools: add tools support for Intel CAT Chao Peng
2015-04-09 10:50   ` Wei Liu
2015-04-16 11:20   ` Ian Campbell
2015-04-09  9:18 ` [PATCH v4 12/12] docs: add xl-psr.markdown Chao Peng
2015-04-09 11:29   ` Andrew Cooper
2015-04-10  7:45     ` Chao Peng
2015-04-16 11:58   ` Ian Campbell
2015-04-17 14:39     ` Chao Peng
2015-04-09 22:15 ` [PATCH v4 00/12] enable Cache Allocation Technology (CAT) for VMs Andrew Cooper

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