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* [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata
@ 2014-12-16 15:03 ` Christophe Leroy
  0 siblings, 0 replies; 7+ messages in thread
From: Christophe Leroy @ 2014-12-16 15:03 UTC (permalink / raw)
  To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
	scottwood
  Cc: linuxppc-dev, linux-kernel

Having a macro will help keep clear code.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

---
 arch/powerpc/kernel/head_8xx.S | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -297,6 +297,17 @@ SystemCall:
  * We have to use the MD_xxx registers for the tablewalk because the
  * equivalent MI_xxx registers only perform the attribute functions.
  */
+
+#ifdef CONFIG_8xx_CPU15
+#define DO_8xx_CPU15(tmp, addr)	\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp;			\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp
+#else
+#define DO_8xx_CPU15(tmp, addr)
+#endif
+
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
 	mtspr	SPRN_DAR, r3
@@ -304,12 +315,7 @@ InstructionTLBMiss:
 	EXCEPTION_PROLOG_0
 	mtspr	SPRN_SPRG_SCRATCH2, r10
 	mfspr	r10, SPRN_SRR0	/* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU15
-	addi	r11, r10, PAGE_SIZE
-	tlbie	r11
-	addi	r11, r10, -PAGE_SIZE
-	tlbie	r11
-#endif
+	DO_8xx_CPU15(r11, r10)
 
 	/* If we are faulting a kernel address, we have to use the
 	 * kernel page tables.
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata
@ 2014-12-16 15:03 ` Christophe Leroy
  0 siblings, 0 replies; 7+ messages in thread
From: Christophe Leroy @ 2014-12-16 15:03 UTC (permalink / raw)
  To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
	scottwood
  Cc: linux-kernel, linuxppc-dev, Joakim Tjernlund

Having a macro will help keep clear code.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

---
 arch/powerpc/kernel/head_8xx.S | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -297,6 +297,17 @@ SystemCall:
  * We have to use the MD_xxx registers for the tablewalk because the
  * equivalent MI_xxx registers only perform the attribute functions.
  */
+
+#ifdef CONFIG_8xx_CPU15
+#define DO_8xx_CPU15(tmp, addr)	\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp;			\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp
+#else
+#define DO_8xx_CPU15(tmp, addr)
+#endif
+
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
 	mtspr	SPRN_DAR, r3
@@ -304,12 +315,7 @@ InstructionTLBMiss:
 	EXCEPTION_PROLOG_0
 	mtspr	SPRN_SPRG_SCRATCH2, r10
 	mfspr	r10, SPRN_SRR0	/* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU15
-	addi	r11, r10, PAGE_SIZE
-	tlbie	r11
-	addi	r11, r10, -PAGE_SIZE
-	tlbie	r11
-#endif
+	DO_8xx_CPU15(r11, r10)
 
 	/* If we are faulting a kernel address, we have to use the
 	 * kernel page tables.
-- 
2.1.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata
@ 2015-04-20  5:26 ` Christophe Leroy
  0 siblings, 0 replies; 7+ messages in thread
From: Christophe Leroy @ 2015-04-20  5:26 UTC (permalink / raw)
  To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
	scottwood
  Cc: linuxppc-dev, linux-kernel

Having a macro will help keep clear code.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

---
 arch/powerpc/kernel/head_8xx.S | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -297,6 +297,17 @@ SystemCall:
  * We have to use the MD_xxx registers for the tablewalk because the
  * equivalent MI_xxx registers only perform the attribute functions.
  */
+
+#ifdef CONFIG_8xx_CPU15
+#define DO_8xx_CPU15(tmp, addr)	\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp;			\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp
+#else
+#define DO_8xx_CPU15(tmp, addr)
+#endif
+
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
 	mtspr	SPRN_DAR, r3
@@ -304,12 +315,7 @@ InstructionTLBMiss:
 	EXCEPTION_PROLOG_0
 	mtspr	SPRN_SPRG_SCRATCH2, r10
 	mfspr	r10, SPRN_SRR0	/* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU15
-	addi	r11, r10, PAGE_SIZE
-	tlbie	r11
-	addi	r11, r10, -PAGE_SIZE
-	tlbie	r11
-#endif
+	DO_8xx_CPU15(r11, r10)
 
 	/* If we are faulting a kernel address, we have to use the
 	 * kernel page tables.
-- 
2.1.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata
@ 2015-04-20  5:26 ` Christophe Leroy
  0 siblings, 0 replies; 7+ messages in thread
From: Christophe Leroy @ 2015-04-20  5:26 UTC (permalink / raw)
  To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
	scottwood
  Cc: linux-kernel, linuxppc-dev, Joakim Tjernlund

Having a macro will help keep clear code.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

---
 arch/powerpc/kernel/head_8xx.S | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b227902e..b3f3cb5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -297,6 +297,17 @@ SystemCall:
  * We have to use the MD_xxx registers for the tablewalk because the
  * equivalent MI_xxx registers only perform the attribute functions.
  */
+
+#ifdef CONFIG_8xx_CPU15
+#define DO_8xx_CPU15(tmp, addr)	\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp;			\
+	addi	tmp, addr, PAGE_SIZE;	\
+	tlbie	tmp
+#else
+#define DO_8xx_CPU15(tmp, addr)
+#endif
+
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
 	mtspr	SPRN_DAR, r3
@@ -304,12 +315,7 @@ InstructionTLBMiss:
 	EXCEPTION_PROLOG_0
 	mtspr	SPRN_SPRG_SCRATCH2, r10
 	mfspr	r10, SPRN_SRR0	/* Get effective address of fault */
-#ifdef CONFIG_8xx_CPU15
-	addi	r11, r10, PAGE_SIZE
-	tlbie	r11
-	addi	r11, r10, -PAGE_SIZE
-	tlbie	r11
-#endif
+	DO_8xx_CPU15(r11, r10)
 
 	/* If we are faulting a kernel address, we have to use the
 	 * kernel page tables.
-- 
2.1.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* RE: [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata
  2015-04-20  5:26 ` Christophe Leroy
@ 2015-04-20 11:40   ` David Laight
  -1 siblings, 0 replies; 7+ messages in thread
From: David Laight @ 2015-04-20 11:40 UTC (permalink / raw)
  To: 'Christophe Leroy', Benjamin Herrenschmidt,
	Paul Mackerras, Michael Ellerman, scottwood@freescale.com
  Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org

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ciwgUEFHRV9TSVpFOwlcDQo+ICsJdGxiaWUJdG1wDQo+ICsjZWxzZQ0KPiArI2RlZmluZSBET184
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aGUgc2FtZSBvYnZpb3VzIGVycm9yIGluIHRoZSBhYm92ZSBiZWZvcmUuDQoNCkknZCBhbHNvIHN1
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YWRkcicgYXQgdGhlIGVuZC4NCg0KCURhdmlkDQoNCg==

^ permalink raw reply	[flat|nested] 7+ messages in thread
* RE: [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata
@ 2015-04-20 11:40   ` David Laight
  0 siblings, 0 replies; 7+ messages in thread
From: David Laight @ 2015-04-20 11:40 UTC (permalink / raw)
  To: 'Christophe Leroy', Benjamin Herrenschmidt,
	Paul Mackerras, Michael Ellerman, scottwood@freescale.com
  Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 960 bytes --]

From: Christophe Leroy
> Sent: 20 April 2015 06:27
> Having a macro will help keep clear code.
...
>   * We have to use the MD_xxx registers for the tablewalk because the
>   * equivalent MI_xxx registers only perform the attribute functions.
>   */
> +
> +#ifdef CONFIG_8xx_CPU15
> +#define DO_8xx_CPU15(tmp, addr)	\
> +	addi	tmp, addr, PAGE_SIZE;	\
> +	tlbie	tmp;			\
> +	addi	tmp, addr, PAGE_SIZE;	\
> +	tlbie	tmp
> +#else
> +#define DO_8xx_CPU15(tmp, addr)
> +#endif

I'm sure I've spotted the same obvious error in the above before.

I'd also suggest calling it 'invalidate_adjacent_pages' - since that it
what it does.

I also guess that the execution time of 'tlbie' is non-trivial.
So you might as well get rid of the temporary register and put an
'addi' to reset 'addr' at the end.

	David

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^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata
  2015-04-20 11:40   ` David Laight
  (?)
@ 2015-04-20 11:43   ` leroy christophe
  -1 siblings, 0 replies; 7+ messages in thread
From: leroy christophe @ 2015-04-20 11:43 UTC (permalink / raw)
  To: David Laight, Benjamin Herrenschmidt, Paul Mackerras,
	Michael Ellerman, scottwood@freescale.com
  Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org



Le 20/04/2015 13:40, David Laight a écrit :
> From: Christophe Leroy
>> Sent: 20 April 2015 06:27
>> Having a macro will help keep clear code.
> ...
>>    * We have to use the MD_xxx registers for the tablewalk because the
>>    * equivalent MI_xxx registers only perform the attribute functions.
>>    */
>> +
>> +#ifdef CONFIG_8xx_CPU15
>> +#define DO_8xx_CPU15(tmp, addr)	\
>> +	addi	tmp, addr, PAGE_SIZE;	\
>> +	tlbie	tmp;			\
>> +	addi	tmp, addr, PAGE_SIZE;	\
>> +	tlbie	tmp
>> +#else
>> +#define DO_8xx_CPU15(tmp, addr)
>> +#endif
> I'm sure I've spotted the same obvious error in the above before.
>
> I'd also suggest calling it 'invalidate_adjacent_pages' - since that it
> what it does.
>
> I also guess that the execution time of 'tlbie' is non-trivial.
> So you might as well get rid of the temporary register and put an
> 'addi' to reset 'addr' at the end.
>
> 	David
>

Forget it, I did a big mistake this morning, involontarily resent an old 
patch.
Sorry for the noise.

Christophe

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-04-20 11:43 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2015-04-20  5:26 [PATCH 07/11] powerpc/8xx: macro for handling CPU15 errata Christophe Leroy
2015-04-20  5:26 ` Christophe Leroy
2015-04-20 11:40 ` David Laight
2015-04-20 11:40   ` David Laight
2015-04-20 11:43   ` leroy christophe
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2014-12-16 15:03 Christophe Leroy
2014-12-16 15:03 ` Christophe Leroy

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