Re: [PATCH 1/6] platform: specify the IOMMU physical translation bit

From: Terje Bergstrom <tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: "nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
	<nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
	Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH 1/6] platform: specify the IOMMU physical translation bit
Date: Mon, 20 Apr 2015 09:35:33 -0700	[thread overview]
Message-ID: <55352AD5.804@nvidia.com> (raw)
In-Reply-To: <CAAVeFuKSY9AvtmjkVY7CApMex3Gq5L5cQ=suaERY5-gtAYai6A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

On 04/20/2015 12:37 AM, Alexandre Courbot wrote:
> I don't have a strong opinion on this - the advantage of a bit mask
> over a bit index is that it at least gives us the option of not having
> a MMU translation bit at all (mask == 0) whereas a bit index of 0 will
> set/unset the first bit.
>
> Not that we need this for now, but keeping that possibility open
> doesn't sound bad for the future (nothing guarantees the GPU will
> always be behind the IOMMU).

We should not rely only on globally enabling / disabling IOMMU. The mask 
you describe is global. We'll want to  bypass IOMMU, but we'll want to 
do that in the mapping code path per buffer. VPR is an example: VPR 
buffers would sometimes be touched by GPU, and GPU needs to bypass 
IOMMU. But interleaved with that GPU is also using normal buffers with 
IOMMU translation.

Of course, sometimes we want to bypass IOMMU globally. So it's good to 
have also a mechanism to disable IOMMU for the whole GPU.

Terje
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