From: Rhyland Klein <rklein@nvidia.com>
To: Benson Leung <bleung@chromium.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Thierry Reding <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>, <linux-clk@vger.kernel.org>,
<linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210
Date: Tue, 5 May 2015 15:55:47 -0400 [thread overview]
Message-ID: <55492043.2010202@nvidia.com> (raw)
In-Reply-To: <CANLzEktX3tiBXvxKgToUr5S7xZ+YibpeG6tDvW1R=qkW6_T5WQ@mail.gmail.com>
On 5/4/2015 7:34 PM, Benson Leung wrote:
> On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein@nvidia.com> wrote:
>> For Tegra210, the logic to calculate out-of-table rates is different
>> from previous generations. Add callbacks that can be overridden to
>> allow for different ways of calculating rates. Default to
>> _cal_rate when not specified.
>
> You should mention that you're adding a new flag and new members that
> may override mdiv as well.
Yes, will add that.
>
>>
>> Based on original work by Aleksandr Frid <afrid@nvidia.com>
>>
>> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
>> ---
>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
>> index 3f92f1ad3961..b63ef31a2d7a 100644
>> --- a/drivers/clk/tegra/clk.h
>> +++ b/drivers/clk/tegra/clk.h
>> @@ -199,6 +199,8 @@ struct div_nmp {
>> * base register.
>> * TEGRA_PLL_BYPASS - PLL has bypass bit
>> * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
>> + * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
>> + * it may be more accurate (especially if SDM present)
>> */
>> struct tegra_clk_pll_params {
>> unsigned long input_min;
>> @@ -235,7 +237,13 @@ struct tegra_clk_pll_params {
>> struct div_nmp *div_nmp;
>> struct tegra_clk_pll_freq_table *freq_table;
>> unsigned long fixed_rate;
>> + bool vco_out;
>
> vco_out is unused and unrelated to this change?
vco_out is used to mark which PLL's have a vco_out, and is going to be
used in the new out-of-table rate calculation in tegra210, so I will
move adding this member until that patch.
>
>> + u16 mdiv_default;
>> + u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
>> void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
>> + int (*calc_rate)(struct clk_hw *hw,
>> + struct tegra_clk_pll_freq_table *cfg,
>> + unsigned long rate, unsigned long parent_rate);
>
> Add kerneldoc for new members.
Will do, thanks!
-rhyland
--
nvpublic
WARNING: multiple messages have this Message-ID (diff)
From: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210
Date: Tue, 5 May 2015 15:55:47 -0400 [thread overview]
Message-ID: <55492043.2010202@nvidia.com> (raw)
In-Reply-To: <CANLzEktX3tiBXvxKgToUr5S7xZ+YibpeG6tDvW1R=qkW6_T5WQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 5/4/2015 7:34 PM, Benson Leung wrote:
> On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> For Tegra210, the logic to calculate out-of-table rates is different
>> from previous generations. Add callbacks that can be overridden to
>> allow for different ways of calculating rates. Default to
>> _cal_rate when not specified.
>
> You should mention that you're adding a new flag and new members that
> may override mdiv as well.
Yes, will add that.
>
>>
>> Based on original work by Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
>> index 3f92f1ad3961..b63ef31a2d7a 100644
>> --- a/drivers/clk/tegra/clk.h
>> +++ b/drivers/clk/tegra/clk.h
>> @@ -199,6 +199,8 @@ struct div_nmp {
>> * base register.
>> * TEGRA_PLL_BYPASS - PLL has bypass bit
>> * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
>> + * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
>> + * it may be more accurate (especially if SDM present)
>> */
>> struct tegra_clk_pll_params {
>> unsigned long input_min;
>> @@ -235,7 +237,13 @@ struct tegra_clk_pll_params {
>> struct div_nmp *div_nmp;
>> struct tegra_clk_pll_freq_table *freq_table;
>> unsigned long fixed_rate;
>> + bool vco_out;
>
> vco_out is unused and unrelated to this change?
vco_out is used to mark which PLL's have a vco_out, and is going to be
used in the new out-of-table rate calculation in tegra210, so I will
move adding this member until that patch.
>
>> + u16 mdiv_default;
>> + u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
>> void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
>> + int (*calc_rate)(struct clk_hw *hw,
>> + struct tegra_clk_pll_freq_table *cfg,
>> + unsigned long rate, unsigned long parent_rate);
>
> Add kerneldoc for new members.
Will do, thanks!
-rhyland
--
nvpublic
next prev parent reply other threads:[~2015-05-05 19:55 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-04 16:37 [PATCH v4 00/20] Tegra210 Clock Support Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 01/20] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 18:05 ` Benson Leung
2015-05-04 18:05 ` Benson Leung
2015-05-07 15:15 ` Thierry Reding
2015-05-07 15:15 ` Thierry Reding
2015-05-07 15:49 ` Rhyland Klein
2015-05-07 15:49 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 02/20] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 19:45 ` Benson Leung
2015-05-04 19:45 ` Benson Leung
2015-05-05 20:14 ` Rhyland Klein
2015-05-05 20:14 ` Rhyland Klein
2015-05-06 13:59 ` Thierry Reding
2015-05-06 16:24 ` Rhyland Klein
2015-05-06 16:24 ` Rhyland Klein
2015-05-04 21:19 ` Andrew Bresticker
2015-05-04 21:19 ` Andrew Bresticker
2015-05-06 11:20 ` Jim Lin
2015-05-06 11:20 ` Jim Lin
2015-05-06 14:15 ` Thierry Reding
2015-05-06 16:20 ` Rhyland Klein
2015-05-06 16:20 ` Rhyland Klein
2015-05-06 14:12 ` Thierry Reding
2015-05-04 16:37 ` [PATCH v4 03/20] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 04/20] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 20:11 ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 05/20] clk: tegra: pll: update warning msg Rhyland Klein
2015-05-04 20:20 ` Benson Leung
2015-05-04 20:20 ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 06/20] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 20:35 ` Benson Leung
2015-05-04 20:35 ` Benson Leung
2015-05-06 14:18 ` Thierry Reding
2015-05-06 14:18 ` Thierry Reding
2015-05-04 16:37 ` [PATCH v4 07/20] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-05-04 21:42 ` Benson Leung
2015-05-04 21:42 ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 08/20] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 23:01 ` Benson Leung
2015-05-04 23:01 ` Benson Leung
2015-05-05 19:16 ` Rhyland Klein
2015-05-05 19:16 ` Rhyland Klein
2015-05-06 13:57 ` Thierry Reding
2015-05-06 16:16 ` Rhyland Klein
2015-05-06 16:16 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 09/20] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 23:11 ` Benson Leung
2015-05-04 23:11 ` Benson Leung
2015-05-05 20:15 ` Rhyland Klein
2015-05-05 20:15 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-05-04 23:34 ` Benson Leung
2015-05-04 23:34 ` Benson Leung
2015-05-05 19:55 ` Rhyland Klein [this message]
2015-05-05 19:55 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 11/20] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-05 17:15 ` Benson Leung
2015-05-04 16:37 ` [PATCH v4 12/20] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-07 15:11 ` Thierry Reding
2015-05-04 16:37 ` [PATCH v4 13/20] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 14/20] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 15/20] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 16/20] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 17/20] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 18/20] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-04 16:37 ` [PATCH v4 19/20] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-04 16:37 ` Rhyland Klein
2015-05-06 14:51 ` Thierry Reding
2015-05-06 16:18 ` Rhyland Klein
2015-05-06 16:18 ` Rhyland Klein
2015-05-06 17:21 ` Rhyland Klein
2015-05-06 17:21 ` Rhyland Klein
2015-05-07 15:16 ` Thierry Reding
2015-05-07 15:16 ` Thierry Reding
2015-05-07 10:39 ` Jim Lin
2015-05-07 10:39 ` Jim Lin
2015-05-07 16:07 ` Rhyland Klein
2015-05-07 16:07 ` Rhyland Klein
2015-05-07 15:18 ` Thierry Reding
2015-05-04 16:37 ` [PATCH v4 20/20] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein
2015-05-05 13:14 ` [PATCH v4 00/20] Tegra210 Clock Support Thierry Reding
2015-05-05 13:14 ` Thierry Reding
2015-05-05 15:55 ` Rhyland Klein
2015-05-05 15:55 ` Rhyland Klein
2015-05-06 13:37 ` Thierry Reding
2015-05-06 16:10 ` Rhyland Klein
2015-05-06 16:10 ` Rhyland Klein
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