diff for duplicates of <554F2AD9.3030005@redhat.com> diff --git a/a/1.txt b/N1/1.txt index f600370..cb59472 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,7 +3,7 @@ Hi, On 10-05-15 11:33, Vishnu Patekar wrote: > Hi, > -> On Sun, May 10, 2015 at 2:23 PM, Hans de Goede <hdegoede@redhat.com> wrote: +> On Sun, May 10, 2015 at 2:23 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote: >> Hi, >> >> On 10-05-15 08:46, Vishnu Patekar wrote: @@ -12,7 +12,7 @@ On 10-05-15 11:33, Vishnu Patekar wrote: >>> sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features >>> e.g. clocks can be added in future. >>> ->>> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com> +>>> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> >> >> >> This seems to only contain stuff which can be shared with the a23 dts, @@ -54,7 +54,7 @@ Hans >>> +/* >>> + * Copyright 2014 Chen-Yu Tsai >>> + * ->>> + * Chen-Yu Tsai <wens@csie.org> +>>> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> >>> + * >>> + * This file is dual-licensed: you can use it either under the terms >>> + * of the GPL or the X11 license, at your option. Note that this dual @@ -104,25 +104,25 @@ Hans >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + ->>> + cpu at 0 { +>>> + cpu@0 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <0>; >>> + }; >>> + ->>> + cpu at 1 { +>>> + cpu@1 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <1>; >>> + }; >>> + ->>> + cpu at 2 { +>>> + cpu@2 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <2>; >>> + }; >>> + ->>> + cpu at 3 { +>>> + cpu@3 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <3>; @@ -142,7 +142,7 @@ Hans >>> + clock-output-names = "pll5"; >>> + }; >>> + ->>> + axi: axi_clk at 01c20050 { +>>> + axi: axi_clk@01c20050 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun8i-a23-axi-clk"; >>> + reg = <0x01c20050 0x4>; @@ -150,7 +150,7 @@ Hans >>> + clock-output-names = "axi"; >>> + }; >>> + ->>> + ahb1_gates: clk at 01c20060 { +>>> + ahb1_gates: clk@01c20060 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; >>> + reg = <0x01c20060 0x8>; @@ -169,7 +169,7 @@ Hans >>> + "ahb1_drc"; >>> + }; >>> + ->>> + apb1_gates: clk at 01c20068 { +>>> + apb1_gates: clk@01c20068 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun8i-a23-apb1-gates-clk"; >>> + reg = <0x01c20068 0x4>; @@ -178,7 +178,7 @@ Hans >>> + "apb1_daudio0", "apb1_daudio1"; >>> + }; >>> + ->>> + apb2: clk at 01c20058 { +>>> + apb2: clk@01c20058 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-apb1-clk"; >>> + reg = <0x01c20058 0x4>; @@ -187,7 +187,7 @@ Hans >>> + clock-output-names = "apb2"; >>> + }; >>> + ->>> + apb2_gates: clk at 01c2006c { +>>> + apb2_gates: clk@01c2006c { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun8i-a23-apb2-gates-clk"; >>> + reg = <0x01c2006c 0x4>; @@ -198,7 +198,7 @@ Hans >>> + "apb2_uart3", "apb2_uart4"; >>> + }; >>> + ->>> + mbus_clk: clk at 01c2015c { +>>> + mbus_clk: clk@01c2015c { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun8i-a23-mbus-clk"; >>> + reg = <0x01c2015c 0x4>; @@ -207,8 +207,8 @@ Hans >>> + }; >>> + }; >>> + ->>> + soc at 01c00000 { ->>> + dma: dma-controller at 01c02000 { +>>> + soc@01c00000 { +>>> + dma: dma-controller@01c02000 { >>> + compatible = "allwinner,sun8i-a23-dma"; >>> + reg = <0x01c02000 0x1000>; >>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -217,33 +217,33 @@ Hans >>> + #dma-cells = <1>; >>> + }; >>> + ->>> + pio: pinctrl at 01c20800 { +>>> + pio: pinctrl@01c20800 { >>> + compatible = "allwinner,sun8i-a33-pinctrl"; >>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; >>> + ->>> + uart0_pins_a: uart0 at 0 { +>>> + uart0_pins_a: uart0@0 { >>> + allwinner,pins = "PF2", "PF4"; >>> + allwinner,function = "uart0"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >>> + }; >>> + ->>> + i2c0_pins_a: i2c0 at 0 { +>>> + i2c0_pins_a: i2c0@0 { >>> + allwinner,pins = "PH2", "PH3"; >>> + allwinner,function = "i2c0"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >>> + }; >>> + ->>> + i2c1_pins_a: i2c1 at 0 { +>>> + i2c1_pins_a: i2c1@0 { >>> + allwinner,pins = "PH4", "PH5"; >>> + allwinner,function = "i2c1"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >>> + }; >>> + ->>> + i2c2_pins_a: i2c2 at 0 { +>>> + i2c2_pins_a: i2c2@0 { >>> + allwinner,pins = "PE12", "PE13"; >>> + allwinner,function = "i2c2"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -251,14 +251,14 @@ Hans >>> + }; >>> + }; >>> + ->>> + lradc: lradc at 01c22800 { +>>> + lradc: lradc@01c22800 { >>> + compatible = "allwinner,sun4i-a10-lradc-keys"; >>> + reg = <0x01c22800 0x100>; >>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; >>> + status = "disabled"; >>> + }; >>> + ->>> + uart4: serial at 01c29000 { +>>> + uart4: serial@01c29000 { >>> + compatible = "snps,dw-apb-uart"; >>> + reg = <0x01c29000 0x400>; >>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index 683fabf..26fc1e0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,10 +2,22 @@ "ref\01431240383-12763-6-git-send-email-vishnupatekar0510@gmail.com\0" "ref\0554F1C95.6060900@redhat.com\0" "ref\0CAEzqOZv034sn-LVcYqrXWukdvcdm=BbVo7gMiYAy-dQG=mpQTw@mail.gmail.com\0" - "From\0hdegoede@redhat.com (Hans de Goede)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" + "ref\0CAEzqOZv034sn-LVcYqrXWukdvcdm=BbVo7gMiYAy-dQG=mpQTw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" "Date\0Sun, 10 May 2015 11:54:33 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>" + emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org + Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> + Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org <linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" "\00:1\0" "b\0" "Hi,\n" @@ -13,7 +25,7 @@ "On 10-05-15 11:33, Vishnu Patekar wrote:\n" "> Hi,\n" ">\n" - "> On Sun, May 10, 2015 at 2:23 PM, Hans de Goede <hdegoede@redhat.com> wrote:\n" + "> On Sun, May 10, 2015 at 2:23 PM, Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:\n" ">> Hi,\n" ">>\n" ">> On 10-05-15 08:46, Vishnu Patekar wrote:\n" @@ -22,7 +34,7 @@ ">>> sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features\n" ">>> e.g. clocks can be added in future.\n" ">>>\n" - ">>> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>\n" + ">>> Signed-off-by: VishnuPatekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" ">>\n" ">>\n" ">> This seems to only contain stuff which can be shared with the a23 dts,\n" @@ -64,7 +76,7 @@ ">>> +/*\n" ">>> + * Copyright 2014 Chen-Yu Tsai\n" ">>> + *\n" - ">>> + * Chen-Yu Tsai <wens@csie.org>\n" + ">>> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>\n" ">>> + *\n" ">>> + * This file is dual-licensed: you can use it either under the terms\n" ">>> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -114,25 +126,25 @@ ">>> + #address-cells = <1>;\n" ">>> + #size-cells = <0>;\n" ">>> +\n" - ">>> + cpu at 0 {\n" + ">>> + cpu@0 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <0>;\n" ">>> + };\n" ">>> +\n" - ">>> + cpu at 1 {\n" + ">>> + cpu@1 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <1>;\n" ">>> + };\n" ">>> +\n" - ">>> + cpu at 2 {\n" + ">>> + cpu@2 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <2>;\n" ">>> + };\n" ">>> +\n" - ">>> + cpu at 3 {\n" + ">>> + cpu@3 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <3>;\n" @@ -152,7 +164,7 @@ ">>> + clock-output-names = \"pll5\";\n" ">>> + };\n" ">>> +\n" - ">>> + axi: axi_clk at 01c20050 {\n" + ">>> + axi: axi_clk@01c20050 {\n" ">>> + #clock-cells = <0>;\n" ">>> + compatible = \"allwinner,sun8i-a23-axi-clk\";\n" ">>> + reg = <0x01c20050 0x4>;\n" @@ -160,7 +172,7 @@ ">>> + clock-output-names = \"axi\";\n" ">>> + };\n" ">>> +\n" - ">>> + ahb1_gates: clk at 01c20060 {\n" + ">>> + ahb1_gates: clk@01c20060 {\n" ">>> + #clock-cells = <1>;\n" ">>> + compatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n" ">>> + reg = <0x01c20060 0x8>;\n" @@ -179,7 +191,7 @@ ">>> + \"ahb1_drc\";\n" ">>> + };\n" ">>> +\n" - ">>> + apb1_gates: clk at 01c20068 {\n" + ">>> + apb1_gates: clk@01c20068 {\n" ">>> + #clock-cells = <1>;\n" ">>> + compatible = \"allwinner,sun8i-a23-apb1-gates-clk\";\n" ">>> + reg = <0x01c20068 0x4>;\n" @@ -188,7 +200,7 @@ ">>> + \"apb1_daudio0\", \"apb1_daudio1\";\n" ">>> + };\n" ">>> +\n" - ">>> + apb2: clk at 01c20058 {\n" + ">>> + apb2: clk@01c20058 {\n" ">>> + #clock-cells = <0>;\n" ">>> + compatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">>> + reg = <0x01c20058 0x4>;\n" @@ -197,7 +209,7 @@ ">>> + clock-output-names = \"apb2\";\n" ">>> + };\n" ">>> +\n" - ">>> + apb2_gates: clk at 01c2006c {\n" + ">>> + apb2_gates: clk@01c2006c {\n" ">>> + #clock-cells = <1>;\n" ">>> + compatible = \"allwinner,sun8i-a23-apb2-gates-clk\";\n" ">>> + reg = <0x01c2006c 0x4>;\n" @@ -208,7 +220,7 @@ ">>> + \"apb2_uart3\", \"apb2_uart4\";\n" ">>> + };\n" ">>> +\n" - ">>> + mbus_clk: clk at 01c2015c {\n" + ">>> + mbus_clk: clk@01c2015c {\n" ">>> + #clock-cells = <0>;\n" ">>> + compatible = \"allwinner,sun8i-a23-mbus-clk\";\n" ">>> + reg = <0x01c2015c 0x4>;\n" @@ -217,8 +229,8 @@ ">>> + };\n" ">>> + };\n" ">>> +\n" - ">>> + soc at 01c00000 {\n" - ">>> + dma: dma-controller at 01c02000 {\n" + ">>> + soc@01c00000 {\n" + ">>> + dma: dma-controller@01c02000 {\n" ">>> + compatible = \"allwinner,sun8i-a23-dma\";\n" ">>> + reg = <0x01c02000 0x1000>;\n" ">>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -227,33 +239,33 @@ ">>> + #dma-cells = <1>;\n" ">>> + };\n" ">>> +\n" - ">>> + pio: pinctrl at 01c20800 {\n" + ">>> + pio: pinctrl@01c20800 {\n" ">>> + compatible = \"allwinner,sun8i-a33-pinctrl\";\n" ">>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,\n" ">>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" ">>> +\n" - ">>> + uart0_pins_a: uart0 at 0 {\n" + ">>> + uart0_pins_a: uart0@0 {\n" ">>> + allwinner,pins = \"PF2\", \"PF4\";\n" ">>> + allwinner,function = \"uart0\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">>> + };\n" ">>> +\n" - ">>> + i2c0_pins_a: i2c0 at 0 {\n" + ">>> + i2c0_pins_a: i2c0@0 {\n" ">>> + allwinner,pins = \"PH2\", \"PH3\";\n" ">>> + allwinner,function = \"i2c0\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">>> + };\n" ">>> +\n" - ">>> + i2c1_pins_a: i2c1 at 0 {\n" + ">>> + i2c1_pins_a: i2c1@0 {\n" ">>> + allwinner,pins = \"PH4\", \"PH5\";\n" ">>> + allwinner,function = \"i2c1\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">>> + };\n" ">>> +\n" - ">>> + i2c2_pins_a: i2c2 at 0 {\n" + ">>> + i2c2_pins_a: i2c2@0 {\n" ">>> + allwinner,pins = \"PE12\", \"PE13\";\n" ">>> + allwinner,function = \"i2c2\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -261,14 +273,14 @@ ">>> + };\n" ">>> + };\n" ">>> +\n" - ">>> + lradc: lradc at 01c22800 {\n" + ">>> + lradc: lradc@01c22800 {\n" ">>> + compatible = \"allwinner,sun4i-a10-lradc-keys\";\n" ">>> + reg = <0x01c22800 0x100>;\n" ">>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n" ">>> + status = \"disabled\";\n" ">>> + };\n" ">>> +\n" - ">>> + uart4: serial at 01c29000 {\n" + ">>> + uart4: serial@01c29000 {\n" ">>> + compatible = \"snps,dw-apb-uart\";\n" ">>> + reg = <0x01c29000 0x400>;\n" ">>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -285,4 +297,4 @@ ">>>\n" >> -ae8d1a62ed7cefd94042141e7273f646bf3a9d35754c5a9ace64e34926c3a4c7 +674b88867e8bbafbb9d747ca8508afd777d6b523d3e34fa7c76d8419bf96bed8
diff --git a/a/1.txt b/N2/1.txt index f600370..a5031a7 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -104,25 +104,25 @@ Hans >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + ->>> + cpu at 0 { +>>> + cpu@0 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <0>; >>> + }; >>> + ->>> + cpu at 1 { +>>> + cpu@1 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <1>; >>> + }; >>> + ->>> + cpu at 2 { +>>> + cpu@2 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <2>; >>> + }; >>> + ->>> + cpu at 3 { +>>> + cpu@3 { >>> + compatible = "arm,cortex-a7"; >>> + device_type = "cpu"; >>> + reg = <3>; @@ -142,7 +142,7 @@ Hans >>> + clock-output-names = "pll5"; >>> + }; >>> + ->>> + axi: axi_clk at 01c20050 { +>>> + axi: axi_clk@01c20050 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun8i-a23-axi-clk"; >>> + reg = <0x01c20050 0x4>; @@ -150,7 +150,7 @@ Hans >>> + clock-output-names = "axi"; >>> + }; >>> + ->>> + ahb1_gates: clk at 01c20060 { +>>> + ahb1_gates: clk@01c20060 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; >>> + reg = <0x01c20060 0x8>; @@ -169,7 +169,7 @@ Hans >>> + "ahb1_drc"; >>> + }; >>> + ->>> + apb1_gates: clk at 01c20068 { +>>> + apb1_gates: clk@01c20068 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun8i-a23-apb1-gates-clk"; >>> + reg = <0x01c20068 0x4>; @@ -178,7 +178,7 @@ Hans >>> + "apb1_daudio0", "apb1_daudio1"; >>> + }; >>> + ->>> + apb2: clk at 01c20058 { +>>> + apb2: clk@01c20058 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-apb1-clk"; >>> + reg = <0x01c20058 0x4>; @@ -187,7 +187,7 @@ Hans >>> + clock-output-names = "apb2"; >>> + }; >>> + ->>> + apb2_gates: clk at 01c2006c { +>>> + apb2_gates: clk@01c2006c { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun8i-a23-apb2-gates-clk"; >>> + reg = <0x01c2006c 0x4>; @@ -198,7 +198,7 @@ Hans >>> + "apb2_uart3", "apb2_uart4"; >>> + }; >>> + ->>> + mbus_clk: clk at 01c2015c { +>>> + mbus_clk: clk@01c2015c { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun8i-a23-mbus-clk"; >>> + reg = <0x01c2015c 0x4>; @@ -207,8 +207,8 @@ Hans >>> + }; >>> + }; >>> + ->>> + soc at 01c00000 { ->>> + dma: dma-controller at 01c02000 { +>>> + soc@01c00000 { +>>> + dma: dma-controller@01c02000 { >>> + compatible = "allwinner,sun8i-a23-dma"; >>> + reg = <0x01c02000 0x1000>; >>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -217,33 +217,33 @@ Hans >>> + #dma-cells = <1>; >>> + }; >>> + ->>> + pio: pinctrl at 01c20800 { +>>> + pio: pinctrl@01c20800 { >>> + compatible = "allwinner,sun8i-a33-pinctrl"; >>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; >>> + ->>> + uart0_pins_a: uart0 at 0 { +>>> + uart0_pins_a: uart0@0 { >>> + allwinner,pins = "PF2", "PF4"; >>> + allwinner,function = "uart0"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >>> + }; >>> + ->>> + i2c0_pins_a: i2c0 at 0 { +>>> + i2c0_pins_a: i2c0@0 { >>> + allwinner,pins = "PH2", "PH3"; >>> + allwinner,function = "i2c0"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >>> + }; >>> + ->>> + i2c1_pins_a: i2c1 at 0 { +>>> + i2c1_pins_a: i2c1@0 { >>> + allwinner,pins = "PH4", "PH5"; >>> + allwinner,function = "i2c1"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >>> + }; >>> + ->>> + i2c2_pins_a: i2c2 at 0 { +>>> + i2c2_pins_a: i2c2@0 { >>> + allwinner,pins = "PE12", "PE13"; >>> + allwinner,function = "i2c2"; >>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -251,14 +251,14 @@ Hans >>> + }; >>> + }; >>> + ->>> + lradc: lradc at 01c22800 { +>>> + lradc: lradc@01c22800 { >>> + compatible = "allwinner,sun4i-a10-lradc-keys"; >>> + reg = <0x01c22800 0x100>; >>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; >>> + status = "disabled"; >>> + }; >>> + ->>> + uart4: serial at 01c29000 { +>>> + uart4: serial@01c29000 { >>> + compatible = "snps,dw-apb-uart"; >>> + reg = <0x01c29000 0x400>; >>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index 683fabf..1f33645 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,10 +2,21 @@ "ref\01431240383-12763-6-git-send-email-vishnupatekar0510@gmail.com\0" "ref\0554F1C95.6060900@redhat.com\0" "ref\0CAEzqOZv034sn-LVcYqrXWukdvcdm=BbVo7gMiYAy-dQG=mpQTw@mail.gmail.com\0" - "From\0hdegoede@redhat.com (Hans de Goede)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" + "From\0Hans de Goede <hdegoede@redhat.com>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI\0" "Date\0Sun, 10 May 2015 11:54:33 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Vishnu Patekar <vishnupatekar0510@gmail.com>\0" + "Cc\0maxime.ripard@free-electrons.com <maxime.ripard@free-electrons.com>" + emilio@elopez.com.ar + Linus Walleij <linus.walleij@linaro.org> + robh+dt@kernel.org <robh+dt@kernel.org> + Chen-Yu Tsai <wens@csie.org> + Jens Kuske <jenskuske@gmail.com> + Arnd Bergmann <arnd@arndb.de> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + linux-sunxi@googlegroups.com <linux-sunxi@googlegroups.com> + " devicetree@vger.kernel.org <devicetree@vger.kernel.org>\0" "\00:1\0" "b\0" "Hi,\n" @@ -114,25 +125,25 @@ ">>> + #address-cells = <1>;\n" ">>> + #size-cells = <0>;\n" ">>> +\n" - ">>> + cpu at 0 {\n" + ">>> + cpu@0 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <0>;\n" ">>> + };\n" ">>> +\n" - ">>> + cpu at 1 {\n" + ">>> + cpu@1 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <1>;\n" ">>> + };\n" ">>> +\n" - ">>> + cpu at 2 {\n" + ">>> + cpu@2 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <2>;\n" ">>> + };\n" ">>> +\n" - ">>> + cpu at 3 {\n" + ">>> + cpu@3 {\n" ">>> + compatible = \"arm,cortex-a7\";\n" ">>> + device_type = \"cpu\";\n" ">>> + reg = <3>;\n" @@ -152,7 +163,7 @@ ">>> + clock-output-names = \"pll5\";\n" ">>> + };\n" ">>> +\n" - ">>> + axi: axi_clk at 01c20050 {\n" + ">>> + axi: axi_clk@01c20050 {\n" ">>> + #clock-cells = <0>;\n" ">>> + compatible = \"allwinner,sun8i-a23-axi-clk\";\n" ">>> + reg = <0x01c20050 0x4>;\n" @@ -160,7 +171,7 @@ ">>> + clock-output-names = \"axi\";\n" ">>> + };\n" ">>> +\n" - ">>> + ahb1_gates: clk at 01c20060 {\n" + ">>> + ahb1_gates: clk@01c20060 {\n" ">>> + #clock-cells = <1>;\n" ">>> + compatible = \"allwinner,sun8i-a23-ahb1-gates-clk\";\n" ">>> + reg = <0x01c20060 0x8>;\n" @@ -179,7 +190,7 @@ ">>> + \"ahb1_drc\";\n" ">>> + };\n" ">>> +\n" - ">>> + apb1_gates: clk at 01c20068 {\n" + ">>> + apb1_gates: clk@01c20068 {\n" ">>> + #clock-cells = <1>;\n" ">>> + compatible = \"allwinner,sun8i-a23-apb1-gates-clk\";\n" ">>> + reg = <0x01c20068 0x4>;\n" @@ -188,7 +199,7 @@ ">>> + \"apb1_daudio0\", \"apb1_daudio1\";\n" ">>> + };\n" ">>> +\n" - ">>> + apb2: clk at 01c20058 {\n" + ">>> + apb2: clk@01c20058 {\n" ">>> + #clock-cells = <0>;\n" ">>> + compatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">>> + reg = <0x01c20058 0x4>;\n" @@ -197,7 +208,7 @@ ">>> + clock-output-names = \"apb2\";\n" ">>> + };\n" ">>> +\n" - ">>> + apb2_gates: clk at 01c2006c {\n" + ">>> + apb2_gates: clk@01c2006c {\n" ">>> + #clock-cells = <1>;\n" ">>> + compatible = \"allwinner,sun8i-a23-apb2-gates-clk\";\n" ">>> + reg = <0x01c2006c 0x4>;\n" @@ -208,7 +219,7 @@ ">>> + \"apb2_uart3\", \"apb2_uart4\";\n" ">>> + };\n" ">>> +\n" - ">>> + mbus_clk: clk at 01c2015c {\n" + ">>> + mbus_clk: clk@01c2015c {\n" ">>> + #clock-cells = <0>;\n" ">>> + compatible = \"allwinner,sun8i-a23-mbus-clk\";\n" ">>> + reg = <0x01c2015c 0x4>;\n" @@ -217,8 +228,8 @@ ">>> + };\n" ">>> + };\n" ">>> +\n" - ">>> + soc at 01c00000 {\n" - ">>> + dma: dma-controller at 01c02000 {\n" + ">>> + soc@01c00000 {\n" + ">>> + dma: dma-controller@01c02000 {\n" ">>> + compatible = \"allwinner,sun8i-a23-dma\";\n" ">>> + reg = <0x01c02000 0x1000>;\n" ">>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -227,33 +238,33 @@ ">>> + #dma-cells = <1>;\n" ">>> + };\n" ">>> +\n" - ">>> + pio: pinctrl at 01c20800 {\n" + ">>> + pio: pinctrl@01c20800 {\n" ">>> + compatible = \"allwinner,sun8i-a33-pinctrl\";\n" ">>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,\n" ">>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" ">>> +\n" - ">>> + uart0_pins_a: uart0 at 0 {\n" + ">>> + uart0_pins_a: uart0@0 {\n" ">>> + allwinner,pins = \"PF2\", \"PF4\";\n" ">>> + allwinner,function = \"uart0\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">>> + };\n" ">>> +\n" - ">>> + i2c0_pins_a: i2c0 at 0 {\n" + ">>> + i2c0_pins_a: i2c0@0 {\n" ">>> + allwinner,pins = \"PH2\", \"PH3\";\n" ">>> + allwinner,function = \"i2c0\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">>> + };\n" ">>> +\n" - ">>> + i2c1_pins_a: i2c1 at 0 {\n" + ">>> + i2c1_pins_a: i2c1@0 {\n" ">>> + allwinner,pins = \"PH4\", \"PH5\";\n" ">>> + allwinner,function = \"i2c1\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">>> + };\n" ">>> +\n" - ">>> + i2c2_pins_a: i2c2 at 0 {\n" + ">>> + i2c2_pins_a: i2c2@0 {\n" ">>> + allwinner,pins = \"PE12\", \"PE13\";\n" ">>> + allwinner,function = \"i2c2\";\n" ">>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -261,14 +272,14 @@ ">>> + };\n" ">>> + };\n" ">>> +\n" - ">>> + lradc: lradc at 01c22800 {\n" + ">>> + lradc: lradc@01c22800 {\n" ">>> + compatible = \"allwinner,sun4i-a10-lradc-keys\";\n" ">>> + reg = <0x01c22800 0x100>;\n" ">>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n" ">>> + status = \"disabled\";\n" ">>> + };\n" ">>> +\n" - ">>> + uart4: serial at 01c29000 {\n" + ">>> + uart4: serial@01c29000 {\n" ">>> + compatible = \"snps,dw-apb-uart\";\n" ">>> + reg = <0x01c29000 0x400>;\n" ">>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -285,4 +296,4 @@ ">>>\n" >> -ae8d1a62ed7cefd94042141e7273f646bf3a9d35754c5a9ace64e34926c3a4c7 +43a1baa37a9e0639f3048c59f6d1f109cb6c39ccfedb9a0f4ffcd40b3fda62f4
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