Re: [Qemu-devel] [PATCH v2] s390x: Add laa and laag instructions

[Alexander Graf <agraf@suse.de>]

On 05/12/2015 10:27 PM, Richard Henderson wrote:
> On 05/12/2015 01:20 PM, Alexander Graf wrote:
>> +static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
>> +{
>> +    /* XXX should reserve the address */
>> +    in2_m2_32s(s, f, o);
>> +}
>> +#define SPEC_in2_m2_32s_atomic 0
>> +
>> +static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
>> +{
>> +    /* XXX should reserve the address */
>> +    in2_m2_64(s, f, o);
>> +}
>> +#define SPEC_in2_m2_64_atomic 0
>> +
> I think these should save the address in o->addr1 so that you don't have to
> recompute it in the wout functions.

But I suppose you basically mean something like this?


Alex

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 73f2de3..8a30c8f 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -4074,25 +4074,17 @@ static void wout_m2_32(DisasContext *s, 
DisasFields *f, DisasOps *o)

  static void wout_m2_32_r1_atomic(DisasContext *s, DisasFields *f, 
DisasOps *o)
  {
-    TCGv_i64 a2 = get_a2(s, f);
-
      /* XXX release reservation */
-    tcg_gen_qemu_st32(o->out, a2, get_mem_index(s));
+    tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
      store_reg32_i64(get_field(f, r1), o->in2);
-
-    tcg_temp_free_i64(a2);
  }
  #define SPEC_wout_m2_32_r1_atomic 0

  static void wout_m2_64_r1_atomic(DisasContext *s, DisasFields *f, 
DisasOps *o)
  {
-    TCGv_i64 a2 = get_a2(s, f);
-
      /* XXX release reservation */
-    tcg_gen_qemu_st64(o->out, a2, get_mem_index(s));
+    tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
      store_reg(get_field(f, r1), o->in2);
-
-    tcg_temp_free_i64(a2);
  }
  #define SPEC_wout_m2_64_r1_atomic 0

@@ -4519,14 +4511,18 @@ static void in2_mri2_64(DisasContext *s, 
DisasFields *f, DisasOps *o)
  static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, 
DisasOps *o)
  {
      /* XXX should reserve the address */
-    in2_m2_32s(s, f, o);
+    o->addr1 = get_a2(s, f);
+    o->in2 = tcg_temp_new_i64();
+    tcg_gen_qemu_ld32s(o->in2, o->addr1, get_mem_index(s));
  }
  #define SPEC_in2_m2_32s_atomic 0

  static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
  {
      /* XXX should reserve the address */
-    in2_m2_64(s, f, o);
+    o->addr1 = get_a2(s, f);
+    o->in2 = tcg_temp_new_i64();
+    tcg_gen_qemu_ld64(o->in2, o->addr1, get_mem_index(s));
  }
  #define SPEC_in2_m2_64_atomic 0