* [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration
@ 2015-05-15 12:07 ` Bill Huang
0 siblings, 0 replies; 6+ messages in thread
From: Bill Huang @ 2015-05-15 12:07 UTC (permalink / raw)
To: pdeschrijver
Cc: mturquette, swarren, thierry.reding, pwalmsley, linux-clk,
linux-tegra, linux-kernel, Bill Huang
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08..734340e 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1630,7 +1630,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
val = pll_readl_base(pll);
if (val & PLL_BASE_ENABLE)
- WARN_ON(val & pll_params->iddq_bit_idx);
+ WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
+ BIT(pll_params->iddq_bit_idx));
else {
int m;
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration
@ 2015-05-15 12:07 ` Bill Huang
0 siblings, 0 replies; 6+ messages in thread
From: Bill Huang @ 2015-05-15 12:07 UTC (permalink / raw)
To: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA
Cc: mturquette-QSEj5FYQhm4dnm+yROfE0A, swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
pwalmsley-DDmLM1+adcrQT0dZR+AlfA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bill Huang
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/clk-pll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08..734340e 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1630,7 +1630,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
val = pll_readl_base(pll);
if (val & PLL_BASE_ENABLE)
- WARN_ON(val & pll_params->iddq_bit_idx);
+ WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
+ BIT(pll_params->iddq_bit_idx));
else {
int m;
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration
@ 2015-05-15 17:12 ` Benson Leung
0 siblings, 0 replies; 6+ messages in thread
From: Benson Leung @ 2015-05-15 17:12 UTC (permalink / raw)
To: Bill Huang
Cc: Peter De Schrijver, Mike Turquette, Stephen Warren,
Thierry Reding, Paul Walmsley, linux-clk, linux-tegra,
linux-kernel@vger.kernel.org
On Fri, May 15, 2015 at 5:07 AM, Bill Huang <bilhuang@nvidia.com> wrote:
> This fixes two things.
>
> - Read the correct IDDQ register
> - Check the correct IDDQ bit position
>
> Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
By the way, does it also make sense to do the same thing for
tegra_clk_register_pllss, which also reads the base register instead
of the specific iddq_reg from params?
> ---
> drivers/clk/tegra/clk-pll.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 05c6d08..734340e 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1630,7 +1630,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
>
> val = pll_readl_base(pll);
> if (val & PLL_BASE_ENABLE)
> - WARN_ON(val & pll_params->iddq_bit_idx);
> + WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
> + BIT(pll_params->iddq_bit_idx));
> else {
> int m;
>
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Benson Leung
Software Engineer, Chrom* OS
bleung@chromium.org
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration
@ 2015-05-15 17:12 ` Benson Leung
0 siblings, 0 replies; 6+ messages in thread
From: Benson Leung @ 2015-05-15 17:12 UTC (permalink / raw)
To: Bill Huang
Cc: Peter De Schrijver, Mike Turquette, Stephen Warren,
Thierry Reding, Paul Walmsley, linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
On Fri, May 15, 2015 at 5:07 AM, Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> This fixes two things.
>
> - Read the correct IDDQ register
> - Check the correct IDDQ bit position
>
> Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Reviewed-by: Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
By the way, does it also make sense to do the same thing for
tegra_clk_register_pllss, which also reads the base register instead
of the specific iddq_reg from params?
> ---
> drivers/clk/tegra/clk-pll.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 05c6d08..734340e 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1630,7 +1630,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
>
> val = pll_readl_base(pll);
> if (val & PLL_BASE_ENABLE)
> - WARN_ON(val & pll_params->iddq_bit_idx);
> + WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
> + BIT(pll_params->iddq_bit_idx));
> else {
> int m;
>
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Benson Leung
Software Engineer, Chrom* OS
bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration
@ 2015-05-18 11:06 ` bilhuang
0 siblings, 0 replies; 6+ messages in thread
From: bilhuang @ 2015-05-18 11:06 UTC (permalink / raw)
To: Benson Leung
Cc: Peter De Schrijver, Mike Turquette, Stephen Warren,
Thierry Reding, Paul Walmsley, linux-clk, linux-tegra,
linux-kernel@vger.kernel.org
On 05/16/2015 01:12 AM, Benson Leung wrote:
> On Fri, May 15, 2015 at 5:07 AM, Bill Huang <bilhuang@nvidia.com> wrote:
>> This fixes two things.
>>
>> - Read the correct IDDQ register
>> - Check the correct IDDQ bit position
>>
>> Signed-off-by: Bill Huang <bilhuang@nvidia.com>
>
> Reviewed-by: Benson Leung <bleung@chromium.org>
>
> By the way, does it also make sense to do the same thing for
> tegra_clk_register_pllss, which also reads the base register instead
> of the specific iddq_reg from params?
>
Yes thanks for catching this, I've sent another fix in
https://patchwork.ozlabs.org/patch/473329/
>> ---
>> drivers/clk/tegra/clk-pll.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
>> index 05c6d08..734340e 100644
>> --- a/drivers/clk/tegra/clk-pll.c
>> +++ b/drivers/clk/tegra/clk-pll.c
>> @@ -1630,7 +1630,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
>>
>> val = pll_readl_base(pll);
>> if (val & PLL_BASE_ENABLE)
>> - WARN_ON(val & pll_params->iddq_bit_idx);
>> + WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
>> + BIT(pll_params->iddq_bit_idx));
>> else {
>> int m;
>>
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration
@ 2015-05-18 11:06 ` bilhuang
0 siblings, 0 replies; 6+ messages in thread
From: bilhuang @ 2015-05-18 11:06 UTC (permalink / raw)
To: Benson Leung
Cc: Peter De Schrijver, Mike Turquette, Stephen Warren,
Thierry Reding, Paul Walmsley, linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
On 05/16/2015 01:12 AM, Benson Leung wrote:
> On Fri, May 15, 2015 at 5:07 AM, Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
>> This fixes two things.
>>
>> - Read the correct IDDQ register
>> - Check the correct IDDQ bit position
>>
>> Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Reviewed-by: Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>
> By the way, does it also make sense to do the same thing for
> tegra_clk_register_pllss, which also reads the base register instead
> of the specific iddq_reg from params?
>
Yes thanks for catching this, I've sent another fix in
https://patchwork.ozlabs.org/patch/473329/
>> ---
>> drivers/clk/tegra/clk-pll.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
>> index 05c6d08..734340e 100644
>> --- a/drivers/clk/tegra/clk-pll.c
>> +++ b/drivers/clk/tegra/clk-pll.c
>> @@ -1630,7 +1630,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
>>
>> val = pll_readl_base(pll);
>> if (val & PLL_BASE_ENABLE)
>> - WARN_ON(val & pll_params->iddq_bit_idx);
>> + WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
>> + BIT(pll_params->iddq_bit_idx));
>> else {
>> int m;
>>
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-05-18 11:06 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2015-05-15 12:07 [PATCH 1/1] clk: tegra: fix WARN_ON in PLL_RE registration Bill Huang
2015-05-15 12:07 ` Bill Huang
2015-05-15 17:12 ` Benson Leung
2015-05-15 17:12 ` Benson Leung
2015-05-18 11:06 ` bilhuang
2015-05-18 11:06 ` bilhuang
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