From: Paul Cercueil <paul@crapouillou.net>
To: Siarhei Volkau <lis8215@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>, kernel test robot <lkp@intel.com>,
kbuild-all@lists.01.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Vinod Koul <vkoul@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Linus Walleij <linus.walleij@linaro.org>,
Jiri Slaby <jirislaby@kernel.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
linux-serial@vger.kernel.org, linux-mips@vger.kernel.org,
GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>
Subject: Re: [PATCH 7/8] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs
Date: Mon, 17 Oct 2022 10:31:53 +0100 [thread overview]
Message-ID: <555WJR.ESJD0KDHOG3S@crapouillou.net> (raw)
In-Reply-To: <CAKNVLfbePJQN07GfhqAs-opm23poWsL0o-DkV=n-f9+H7Y7rpg@mail.gmail.com>
Hi Siarhei,
Le dim., oct. 16 2022 at 21:39:48 +0300, Siarhei Volkau
<lis8215@gmail.com> a écrit :
> чт, 13 окт. 2022 г. в 21:56, Siarhei Volkau
> <lis8215@gmail.com>:
>
>> > Just disable the divider in ingenic_fixup_fdt() in
>
>> I'll check that.
>
> I checked that approach: serial seems to be working as expected,
> but not all the time: there's a time period when the CGU driver
> started but serial console driver is still early one.
> In my case UART produces garbage at that period since CGU
> needs to enable clock divider back: ext is 24MHz but 12MHz
> required for audio codec and USB to function properly.
What I'd do, is just force-enable it to 12 MHz in ingenic_fixup_fdt(),
since the programming manual basically says that 24 MHz does not work
properly.
Then in the earlycon setup code hardcode the /2 divider with a big fat
comment about why it's there.
Cheers,
-Paul
> So I think Arnd's approach:
>
>> the hardware should already be in a working state,
>> with no need to touch it during early boot.
>
> shall resolve the problem, although I can't check it on all supported
> hardware.
>
> BR,
> Siarhei
WARNING: multiple messages have this Message-ID (diff)
From: Paul Cercueil <paul@crapouillou.net>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH 7/8] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs
Date: Mon, 17 Oct 2022 10:31:53 +0100 [thread overview]
Message-ID: <555WJR.ESJD0KDHOG3S@crapouillou.net> (raw)
In-Reply-To: <CAKNVLfbePJQN07GfhqAs-opm23poWsL0o-DkV=n-f9+H7Y7rpg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]
Hi Siarhei,
Le dim., oct. 16 2022 at 21:39:48 +0300, Siarhei Volkau
<lis8215@gmail.com> a écrit :
> чт, 13 окт. 2022 г. в 21:56, Siarhei Volkau
> <lis8215@gmail.com>:
>
>> > Just disable the divider in ingenic_fixup_fdt() in
>
>> I'll check that.
>
> I checked that approach: serial seems to be working as expected,
> but not all the time: there's a time period when the CGU driver
> started but serial console driver is still early one.
> In my case UART produces garbage at that period since CGU
> needs to enable clock divider back: ext is 24MHz but 12MHz
> required for audio codec and USB to function properly.
What I'd do, is just force-enable it to 12 MHz in ingenic_fixup_fdt(),
since the programming manual basically says that 24 MHz does not work
properly.
Then in the earlycon setup code hardcode the /2 divider with a big fat
comment about why it's there.
Cheers,
-Paul
> So I think Arnd's approach:
>
>> the hardware should already be in a working state,
>> with no need to touch it during early boot.
>
> shall resolve the problem, although I can't check it on all supported
> hardware.
>
> BR,
> Siarhei
next prev parent reply other threads:[~2022-10-17 9:32 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-09 18:13 [PATCH 0/8] MIPS: ingenic: Add support for the JZ4755 SoC Siarhei Volkau
2022-10-09 18:13 ` [PATCH 1/8] dt-bindings: " Siarhei Volkau
2022-10-10 14:53 ` Krzysztof Kozlowski
2022-10-10 20:18 ` Siarhei Volkau
2022-10-11 12:08 ` Krzysztof Kozlowski
2022-10-13 9:03 ` Paul Cercueil
2022-10-09 18:13 ` [PATCH 2/8] MIPS: ingenic: add new machine type MACH_JZ4755 Siarhei Volkau
2022-10-09 18:13 ` [PATCH 3/8] dt-bindings: clock: Add Ingenic JZ4755 CGU header Siarhei Volkau
2022-10-10 13:05 ` Rob Herring
2022-10-09 18:13 ` [PATCH 4/8] clk: Add Ingenic JZ4755 CGU driver Siarhei Volkau
2022-10-10 19:24 ` kernel test robot
2022-10-09 18:13 ` [PATCH 5/8] pinctrl: ingenic: JZ4755 minor bug fixes Siarhei Volkau
2022-10-17 9:46 ` Linus Walleij
2022-10-09 18:13 ` [PATCH 6/8] dmaengine: JZ4780: Add support for the JZ4755 Siarhei Volkau
2022-10-09 18:13 ` [PATCH 7/8] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs Siarhei Volkau
2022-10-09 22:28 ` kernel test robot
2022-10-13 6:37 ` Siarhei Volkau
2022-10-13 6:37 ` Siarhei Volkau
2022-10-13 6:46 ` Arnd Bergmann
2022-10-13 6:46 ` Arnd Bergmann
2022-10-13 9:17 ` Paul Cercueil
2022-10-13 9:17 ` Paul Cercueil
2022-10-13 18:56 ` Siarhei Volkau
2022-10-13 18:56 ` Siarhei Volkau
2022-10-16 18:39 ` Siarhei Volkau
2022-10-16 18:39 ` Siarhei Volkau
2022-10-17 9:31 ` Paul Cercueil [this message]
2022-10-17 9:31 ` Paul Cercueil
2022-10-19 15:19 ` Siarhei Volkau
2022-10-19 15:19 ` Siarhei Volkau
2022-10-10 16:12 ` kernel test robot
2022-10-10 20:20 ` Greg Kroah-Hartman
2022-10-11 18:38 ` Siarhei Volkau
2022-10-10 21:39 ` kernel test robot
2022-10-09 18:13 ` [PATCH 8/8] MIPS: DTS: Ingenic: Add support for the JZ4755 SoC Siarhei Volkau
2022-10-10 14:54 ` Krzysztof Kozlowski
2022-10-10 20:00 ` Siarhei Volkau
2022-10-11 12:09 ` Krzysztof Kozlowski
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