Re: [PATCH RFC v2 01/10] MIPS: Add SysRq operation to dump TLBs on all CPUs

[Joshua Kinard <kumba@gentoo.org>]

On 05/19/2015 04:50, James Hogan wrote:
> Add a MIPS specific SysRq operation to dump the TLB entries on all CPUs,
> using the 'x' trigger key.

Thought: Would it make sense to split apart the data such that one SysRq key
dumps the CP0 registers of all CPUs, and another dumps the TLB info?


> +/*
> + * Dump TLB entries on all CPUs.
> + */
> +
> +static DEFINE_SPINLOCK(show_lock);
> +
> +static void sysrq_tlbdump_single(void *dummy)
> +{
> +	const int field = 2 * sizeof(unsigned long);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&show_lock, flags);
> +
> +	pr_info("CPU%d:\n", smp_processor_id());
> +	pr_info("Index	: %0x\n", read_c0_index());
> +	pr_info("Pagemask: %0x\n", read_c0_pagemask());
> +	pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
> +	pr_info("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
> +	pr_info("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
> +	pr_info("Wired   : %0x\n", read_c0_wired());
> +	pr_info("Pagegrain: %0x\n", read_c0_pagegrain());
> +	if (cpu_has_htw) {
> +		pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
> +		pr_info("PWSize  : %0*lx\n", field, read_c0_pwsize());
> +		pr_info("PWCtl   : %0x\n", read_c0_pwctl());
> +	}
> +	pr_info("\n");
> +	dump_tlb_all();
> +	pr_info("\n");
> +
> +	spin_unlock_irqrestore(&show_lock, flags);
> +}

The older CPUs, like the R10000 don't have a PageGrain register I believe (at
least R10K doesn't),  Does that need to be stuffed behind a conditional?  Also,
R10K (and newer?) CPUs have a FrameMask CP0 register ($21).  Linux currently
scribbles a 0 to the writable bits, though, so I'm not sure if it matters.

--J