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From: Leon Alrae <leon.alrae@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, afaerber@suse.de, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v7 0/3] target-mips: Add support for misaligned accesses
Date: Tue, 2 Jun 2015 10:49:03 +0100	[thread overview]
Message-ID: <556D7C0F.3000509@imgtec.com> (raw)
In-Reply-To: <1433157204-19708-1-git-send-email-yongbok.kim@imgtec.com>

On 01/06/2015 12:13, Yongbok Kim wrote:
> This patch set adds support for misaligned memory accesses in MIPS architecture
> Release 6 and MIPS SIMD Architecture.
> 
> The behaviour, semantics, and architecture specifications of misaligned memory
> accesses are described in:
> MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS64
> Architecture, Appendix B Misaligned Memory Accesses.
> Available at http://www.imgtec.com/mips/architectures/mips64.asp
> 
> Regards,
> Yongbok
> 
> v7:
> * Rephrased comments (Peter)
> * Reverted changes for LDPC/LWPC (Leon)
> * Fixed cosmetic issues (Leon)
> 
> v6:
> * Rephrased comments (Peter)
> 
> v5:
> * Rewrote R6 patch to use new MO_UNALIN (Richard)
> * Further cleanup to pass caculated address for MSA LD/ ST (Richard)
> 
> v4: 
> * Removed the work-around per the recent TCG change for misaligned accesses
> * Added probe_write() (Richard)
> * Used helper_ret_*_mmu directly (Richard)
> * Removed TLB checking for MSA LD (Richard)
> * Removed unnecessary save_cpu_state() calls
> 
> v3:
> * Rewrote MSA patch
> * Work-around is using byte-to-byte accesses and endianness corrections for 
>   R5+MSA. (This replaces the misaligned flag from v2.) (Leon)
> * Bug fixes (Leon)
> * Separate helper functions for each data formats
> 
> v2:
> * Removed re-translation in the mips_cpu_do_unaligned_access() (Peter)
> * Checks validity only if an access is spanning into two pages in MSA (Leon)
> * Introduced misaligned flag to indicate MSA ld/st is ongoing, is used to
>   allow misaligned accesses in the mips_cpu_do_unaligned_access() callback.
>   This is crucial to support MSA misaligned accesses in Release 5 cores.
> 
> Yongbok Kim (3):
>   target-mips: Misaligned memory accesses for R6
>   softmmu: Add probe_write()
>   target-mips: Misaligned memory accesses for MSA
> 
>  include/exec/exec-all.h      |    2 +
>  softmmu_template.h           |   22 +++++++
>  target-mips/helper.h         |   10 +++-
>  target-mips/op_helper.c      |  136 ++++++++++++++++++++++-------------------
>  target-mips/translate.c      |   66 ++++++++++++++-------
>  target-mips/translate_init.c |    2 +-
>  6 files changed, 150 insertions(+), 88 deletions(-)
> 

The series looks good to me:

Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>

Thanks,
Leon

PS: I've just noticed that some of do_*() functions are unused now, so
they should be removed. I'll do that while applying to mips-next.

      parent reply	other threads:[~2015-06-02  9:49 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-01 11:13 [Qemu-devel] [PATCH v7 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
2015-06-01 11:13 ` [Qemu-devel] [PATCH v7 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
2015-06-01 11:13 ` [Qemu-devel] [PATCH v7 2/3] softmmu: Add probe_write() Yongbok Kim
2015-06-01 11:13 ` [Qemu-devel] [PATCH v7 3/3] target-mips: Misaligned memory accesses for MSA Yongbok Kim
2015-06-02  9:49 ` Leon Alrae [this message]

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