Re: PCI Pass-through in Xen ARM - Draft 2.

[Julien Grall <julien.grall@citrix.com>]

On 29/06/15 11:50, Ian Campbell wrote:
> On Mon, 2015-06-29 at 11:31 +0100, Julien Grall wrote:
>> Hi Manish,
>>
>> On 28/06/15 19:38, Manish Jaggi wrote:
>>> 4.1 Holes in guest memory space
>>> ----------------------------
>>> Holes are added in the guest memory space for mapping pci device's BAR
>>> regions.
>>> These are defined in arch-arm.h
>>>
>>> /* For 32bit */
>>> GUEST_MMIO_HOLE0_BASE, GUEST_MMIO_HOLE0_SIZE
>>>  
>>> /* For 64bit */
>>> GUEST_MMIO_HOLE1_BASE , GUEST_MMIO_HOLE1_SIZE
>>
>> The memory layout for 32bit and 64bit are exactly the same. Why do you
>> need to differ here?
> 
> I took this to be a "hole under 4GB" and a "hole over 4GB" IOW rather
> than specific to 32-bit/64-bit guests it is specific to 32/64 bit
> devices, the latter of which could be placed higher in RAM, which is
> useful since the space under 4GB is naturally more limited.

I wasn't able to deduce that with this section. It needs a minimum of
explanation based on what you just said.

That also bring the question about 64 bit PCI and short page table. Do
we support it (i.e possibility to allocate 64 bit BAR below 4GB)?

I don't mind the answer, but it needs to be clarify for the implementation.

Regards,

-- 
Julien Grall