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From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Jonathan Bell <jonathan-FnsA7b+Nu9XbIbC87yuRow@public.gmane.org>,
	Linus Walleij
	<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Lee Jones <lee-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-gpio <linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	linux-rpi-kernel
	<linux-rpi-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: Re: [PATCH] pinctrl: bcm2835: Clear the event latch register when disabling interrupts
Date: Fri, 10 Jul 2015 22:15:40 -0600	[thread overview]
Message-ID: <55A0986C.1030905@wwwdotorg.org> (raw)
In-Reply-To: <55927F0B.80602-FnsA7b+Nu9XbIbC87yuRow@public.gmane.org>

On 06/30/2015 05:35 AM, Jonathan Bell wrote:
> It's possible to hit a race condition if interrupts are generated on a GPIO
> pin when the IRQ line in question is being disabled.
> 
> If the interrupt is freed, bcm2835_gpio_irq_disable() is called which
> disables the event generation sources (edge, level). If an event occurred
> between the last disabling of hard IRQs and the write to the event
> source registers, a bit would be set in the GPIO event detect register
> (GPEDSn) which goes unacknowledged by bcm2835_gpio_irq_handler()
> so Linux complains loudly.
> 
> There is no per-GPIO mask register, so when disabling GPIO interrupts
> write 1 to the relevant bit in GPEDSn to clear out any stale events.

Acked-by: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>

(Sorry for the slow response; I was on vacation)

  parent reply	other threads:[~2015-07-11  4:15 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-30 11:35 [PATCH] pinctrl: bcm2835: Clear the event latch register when disabling interrupts Jonathan Bell
     [not found] ` <55927F0B.80602-FnsA7b+Nu9XbIbC87yuRow@public.gmane.org>
2015-07-11  4:15   ` Stephen Warren [this message]
2015-07-16 13:33 ` Linus Walleij

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