* [PATCH 0/7] Initial SMP/CPS 64-bit support
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras
Hi,
This patchset fixes build problems on 64-bit kernels when SMP/CPS is
enabled. This is preparatory work for MIPS R6 SMP/CPS support but it allows the
CPS code to be build tested on 64-bit configurations.
Markos Chandras (7):
MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer
casting
MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA
MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2
MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit
MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0
MIPS: kernel: cps-vec: Use macros for various arithmetics and memory
operations
Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit"
arch/mips/Kconfig | 2 +-
arch/mips/kernel/cps-vec.S | 96 +++++++++++++++++++++++-----------------------
arch/mips/kernel/smp-cps.c | 6 +--
3 files changed, 52 insertions(+), 52 deletions(-)
--
2.4.5
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 1/7] MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer casting
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
Commit 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") added hotplug
support in the SMP/CPS implementation but it introduced a few build problems
on 64-bit kernels due to pointer being casted to and from 'int' C types. We
fix this problem by using 'unsigned long' instead which should match the size
of the pointers in 32/64-bit kernels. Finally, we fix the comment since the
CM base address is loaded to v1($3) instead of v0.
Fixes the following build problems:
arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt':
arch/mips/kernel/smp-cps.c:366:17: error: cast from pointer to integer of
different size [-Werror=pointer-to-int-cast]
[...]
arch/mips/kernel/smp-cps.c: In function 'cps_cpu_die':
arch/mips/kernel/smp-cps.c:427:13: error: cast to pointer
from integer of different size [-Werror=int-to-pointer-cast]
cc1: all warnings being treated as errors
Fixes: 1d8f1f5a780a ("MIPS: smp-cps: hotplug support")
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/smp-cps.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 4251d390b5b6..c88937745b4e 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -133,7 +133,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
/*
* Patch the start of mips_cps_core_entry to provide:
*
- * v0 = CM base address
+ * v1 = CM base address
* s0 = kseg0 CCA
*/
entry_code = (u32 *)&mips_cps_core_entry;
@@ -369,7 +369,7 @@ void play_dead(void)
static void wait_for_sibling_halt(void *ptr_cpu)
{
- unsigned cpu = (unsigned)ptr_cpu;
+ unsigned cpu = (unsigned long)ptr_cpu;
unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
unsigned halted;
unsigned long flags;
@@ -430,7 +430,7 @@ static void cps_cpu_die(unsigned int cpu)
*/
err = smp_call_function_single(cpu_death_sibling,
wait_for_sibling_halt,
- (void *)cpu, 1);
+ (void *)(unsigned long)cpu, 1);
if (err)
panic("Failed to call remote sibling CPU\n");
}
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 1/7] MIPS: kernel: smp-cps: Fix 64-bit compatibility errors due to pointer casting
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
Commit 1d8f1f5a780a ("MIPS: smp-cps: hotplug support") added hotplug
support in the SMP/CPS implementation but it introduced a few build problems
on 64-bit kernels due to pointer being casted to and from 'int' C types. We
fix this problem by using 'unsigned long' instead which should match the size
of the pointers in 32/64-bit kernels. Finally, we fix the comment since the
CM base address is loaded to v1($3) instead of v0.
Fixes the following build problems:
arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt':
arch/mips/kernel/smp-cps.c:366:17: error: cast from pointer to integer of
different size [-Werror=pointer-to-int-cast]
[...]
arch/mips/kernel/smp-cps.c: In function 'cps_cpu_die':
arch/mips/kernel/smp-cps.c:427:13: error: cast to pointer
from integer of different size [-Werror=int-to-pointer-cast]
cc1: all warnings being treated as errors
Fixes: 1d8f1f5a780a ("MIPS: smp-cps: hotplug support")
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/smp-cps.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 4251d390b5b6..c88937745b4e 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -133,7 +133,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
/*
* Patch the start of mips_cps_core_entry to provide:
*
- * v0 = CM base address
+ * v1 = CM base address
* s0 = kseg0 CCA
*/
entry_code = (u32 *)&mips_cps_core_entry;
@@ -369,7 +369,7 @@ void play_dead(void)
static void wait_for_sibling_halt(void *ptr_cpu)
{
- unsigned cpu = (unsigned)ptr_cpu;
+ unsigned cpu = (unsigned long)ptr_cpu;
unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
unsigned halted;
unsigned long flags;
@@ -430,7 +430,7 @@ static void cps_cpu_die(unsigned int cpu)
*/
err = smp_call_function_single(cpu_death_sibling,
wait_for_sibling_halt,
- (void *)cpu, 1);
+ (void *)(unsigned long)cpu, 1);
if (err)
panic("Failed to call remote sibling CPU\n");
}
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/7] MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
The PTR_LA macro will pick the correct "la" or "dla" macro to
load an address to a register. This gets rids of the following
warnings (and others) when building a 64-bit CPS kernel:
arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address
[...]
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 55b759a0019e..a4b2d81f45dd 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -60,7 +60,7 @@ LEAF(mips_cps_core_entry)
nop
/* This is an NMI */
- la k0, nmi_handler
+ PTR_LA k0, nmi_handler
jr k0
nop
@@ -156,7 +156,7 @@ dcache_done:
ehb
/* Jump to kseg0 */
- la t0, 1f
+ PTR_LA t0, 1f
jr t0
nop
@@ -217,7 +217,7 @@ LEAF(excep_intex)
.org 0x480
LEAF(excep_ejtag)
- la k0, ejtag_debug_handler
+ PTR_LA k0, ejtag_debug_handler
jr k0
nop
END(excep_ejtag)
@@ -237,7 +237,7 @@ LEAF(mips_cps_core_init)
/* ...and for the moment only 1 VPE */
dvpe
- la t1, 1f
+ PTR_LA t1, 1f
jr.hb t1
nop
@@ -298,14 +298,14 @@ LEAF(mips_cps_core_init)
LEAF(mips_cps_boot_vpes)
/* Retrieve CM base address */
- la t0, mips_cm_base
+ PTR_LA t0, mips_cm_base
lw t0, 0(t0)
/* Calculate a pointer to this cores struct core_boot_config */
lw t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
- la t1, mips_cps_core_bootcfg
+ PTR_LA t1, mips_cps_core_bootcfg
lw t1, 0(t1)
addu t0, t0, t1
@@ -351,7 +351,7 @@ LEAF(mips_cps_boot_vpes)
1: /* Enter VPE configuration state */
dvpe
- la t1, 1f
+ PTR_LA t1, 1f
jr.hb t1
nop
1: mfc0 t1, CP0_MVPCONTROL
@@ -445,7 +445,7 @@ LEAF(mips_cps_boot_vpes)
/* This VPE should be offline, halt the TC */
li t0, TCHALT_H
mtc0 t0, CP0_TCHALT
- la t0, 1f
+ PTR_LA t0, 1f
1: jr.hb t0
nop
@@ -466,10 +466,10 @@ LEAF(mips_cps_boot_vpes)
.set noat
lw $1, TI_CPU(gp)
sll $1, $1, LONGLOG
- la \dest, __per_cpu_offset
+ PTR_LA \dest, __per_cpu_offset
addu $1, $1, \dest
lw $1, 0($1)
- la \dest, cps_cpu_state
+ PTR_LA \dest, cps_cpu_state
addu \dest, \dest, $1
.set pop
.endm
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/7] MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
The PTR_LA macro will pick the correct "la" or "dla" macro to
load an address to a register. This gets rids of the following
warnings (and others) when building a 64-bit CPS kernel:
arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address
[...]
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 55b759a0019e..a4b2d81f45dd 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -60,7 +60,7 @@ LEAF(mips_cps_core_entry)
nop
/* This is an NMI */
- la k0, nmi_handler
+ PTR_LA k0, nmi_handler
jr k0
nop
@@ -156,7 +156,7 @@ dcache_done:
ehb
/* Jump to kseg0 */
- la t0, 1f
+ PTR_LA t0, 1f
jr t0
nop
@@ -217,7 +217,7 @@ LEAF(excep_intex)
.org 0x480
LEAF(excep_ejtag)
- la k0, ejtag_debug_handler
+ PTR_LA k0, ejtag_debug_handler
jr k0
nop
END(excep_ejtag)
@@ -237,7 +237,7 @@ LEAF(mips_cps_core_init)
/* ...and for the moment only 1 VPE */
dvpe
- la t1, 1f
+ PTR_LA t1, 1f
jr.hb t1
nop
@@ -298,14 +298,14 @@ LEAF(mips_cps_core_init)
LEAF(mips_cps_boot_vpes)
/* Retrieve CM base address */
- la t0, mips_cm_base
+ PTR_LA t0, mips_cm_base
lw t0, 0(t0)
/* Calculate a pointer to this cores struct core_boot_config */
lw t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
- la t1, mips_cps_core_bootcfg
+ PTR_LA t1, mips_cps_core_bootcfg
lw t1, 0(t1)
addu t0, t0, t1
@@ -351,7 +351,7 @@ LEAF(mips_cps_boot_vpes)
1: /* Enter VPE configuration state */
dvpe
- la t1, 1f
+ PTR_LA t1, 1f
jr.hb t1
nop
1: mfc0 t1, CP0_MVPCONTROL
@@ -445,7 +445,7 @@ LEAF(mips_cps_boot_vpes)
/* This VPE should be offline, halt the TC */
li t0, TCHALT_H
mtc0 t0, CP0_TCHALT
- la t0, 1f
+ PTR_LA t0, 1f
1: jr.hb t0
nop
@@ -466,10 +466,10 @@ LEAF(mips_cps_boot_vpes)
.set noat
lw $1, TI_CPU(gp)
sll $1, $1, LONGLOG
- la \dest, __per_cpu_offset
+ PTR_LA \dest, __per_cpu_offset
addu $1, $1, \dest
lw $1, 0($1)
- la \dest, cps_cpu_state
+ PTR_LA \dest, cps_cpu_state
addu \dest, \dest, $1
.set pop
.endm
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/7] MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2
in preparation for 64-bit CPS support.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index a4b2d81f45dd..bbbd88e994f0 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -229,7 +229,7 @@ LEAF(mips_cps_core_init)
nop
.set push
- .set mips32r2
+ .set mips64r2
.set mt
/* Only allow 1 TC per VPE to execute... */
@@ -346,7 +346,7 @@ LEAF(mips_cps_boot_vpes)
nop
.set push
- .set mips32r2
+ .set mips64r2
.set mt
1: /* Enter VPE configuration state */
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/7] MIPS: kernel: cps-vec: Replace mips32r2 ISA level with mips64r2
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2
in preparation for 64-bit CPS support.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index a4b2d81f45dd..bbbd88e994f0 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -229,7 +229,7 @@ LEAF(mips_cps_core_init)
nop
.set push
- .set mips32r2
+ .set mips64r2
.set mt
/* Only allow 1 TC per VPE to execute... */
@@ -346,7 +346,7 @@ LEAF(mips_cps_boot_vpes)
nop
.set push
- .set mips32r2
+ .set mips64r2
.set mt
1: /* Enter VPE configuration state */
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/7] MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This
breaks the build on 64-bit. As a result of which, use the pseudo-registers
ta0-ta3 to make the code compatible with 64-bit.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 42 +++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index bbbd88e994f0..21f714a81ebd 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -250,25 +250,25 @@ LEAF(mips_cps_core_init)
mfc0 t0, CP0_MVPCONF0
srl t0, t0, MVPCONF0_PVPE_SHIFT
andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
- addiu t7, t0, 1
+ addiu ta3, t0, 1
/* If there's only 1, we're done */
beqz t0, 2f
nop
/* Loop through each VPE within this core */
- li t5, 1
+ li ta1, 1
1: /* Operate on the appropriate TC */
- mtc0 t5, CP0_VPECONTROL
+ mtc0 ta1, CP0_VPECONTROL
ehb
/* Bind TC to VPE (1:1 TC:VPE mapping) */
- mttc0 t5, CP0_TCBIND
+ mttc0 ta1, CP0_TCBIND
/* Set exclusive TC, non-active, master */
li t0, VPECONF0_MVP
- sll t1, t5, VPECONF0_XTC_SHIFT
+ sll t1, ta1, VPECONF0_XTC_SHIFT
or t0, t0, t1
mttc0 t0, CP0_VPECONF0
@@ -280,8 +280,8 @@ LEAF(mips_cps_core_init)
mttc0 t0, CP0_TCHALT
/* Next VPE */
- addiu t5, t5, 1
- slt t0, t5, t7
+ addiu ta1, ta1, 1
+ slt t0, ta1, ta3
bnez t0, 1b
nop
@@ -310,7 +310,7 @@ LEAF(mips_cps_boot_vpes)
addu t0, t0, t1
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
- has_mt t6, 1f
+ has_mt ta2, 1f
li t9, 0
/* Find the number of VPEs present in the core */
@@ -334,13 +334,13 @@ LEAF(mips_cps_boot_vpes)
1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
li t1, VPEBOOTCFG_SIZE
mul v0, t9, t1
- lw t7, COREBOOTCFG_VPECONFIG(t0)
- addu v0, v0, t7
+ lw ta3, COREBOOTCFG_VPECONFIG(t0)
+ addu v0, v0, ta3
#ifdef CONFIG_MIPS_MT
/* If the core doesn't support MT then return */
- bnez t6, 1f
+ bnez ta2, 1f
nop
jr ra
nop
@@ -360,12 +360,12 @@ LEAF(mips_cps_boot_vpes)
ehb
/* Loop through each VPE */
- lw t6, COREBOOTCFG_VPEMASK(t0)
- move t8, t6
- li t5, 0
+ lw ta2, COREBOOTCFG_VPEMASK(t0)
+ move t8, ta2
+ li ta1, 0
/* Check whether the VPE should be running. If not, skip it */
-1: andi t0, t6, 1
+1: andi t0, ta2, 1
beqz t0, 2f
nop
@@ -373,7 +373,7 @@ LEAF(mips_cps_boot_vpes)
mfc0 t0, CP0_VPECONTROL
ori t0, t0, VPECONTROL_TARGTC
xori t0, t0, VPECONTROL_TARGTC
- or t0, t0, t5
+ or t0, t0, ta1
mtc0 t0, CP0_VPECONTROL
ehb
@@ -384,8 +384,8 @@ LEAF(mips_cps_boot_vpes)
/* Calculate a pointer to the VPEs struct vpe_boot_config */
li t0, VPEBOOTCFG_SIZE
- mul t0, t0, t5
- addu t0, t0, t7
+ mul t0, t0, ta1
+ addu t0, t0, ta3
/* Set the TC restart PC */
lw t1, VPEBOOTCFG_PC(t0)
@@ -423,9 +423,9 @@ LEAF(mips_cps_boot_vpes)
mttc0 t0, CP0_VPECONF0
/* Next VPE */
-2: srl t6, t6, 1
- addiu t5, t5, 1
- bnez t6, 1b
+2: srl ta2, ta2, 1
+ addiu ta1, ta1, 1
+ bnez ta2, 1b
nop
/* Leave VPE configuration state */
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/7] MIPS: kernel: cps-vec: Use ta0-ta3 pseudo-registers for 64-bit
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This
breaks the build on 64-bit. As a result of which, use the pseudo-registers
ta0-ta3 to make the code compatible with 64-bit.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 42 +++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index bbbd88e994f0..21f714a81ebd 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -250,25 +250,25 @@ LEAF(mips_cps_core_init)
mfc0 t0, CP0_MVPCONF0
srl t0, t0, MVPCONF0_PVPE_SHIFT
andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
- addiu t7, t0, 1
+ addiu ta3, t0, 1
/* If there's only 1, we're done */
beqz t0, 2f
nop
/* Loop through each VPE within this core */
- li t5, 1
+ li ta1, 1
1: /* Operate on the appropriate TC */
- mtc0 t5, CP0_VPECONTROL
+ mtc0 ta1, CP0_VPECONTROL
ehb
/* Bind TC to VPE (1:1 TC:VPE mapping) */
- mttc0 t5, CP0_TCBIND
+ mttc0 ta1, CP0_TCBIND
/* Set exclusive TC, non-active, master */
li t0, VPECONF0_MVP
- sll t1, t5, VPECONF0_XTC_SHIFT
+ sll t1, ta1, VPECONF0_XTC_SHIFT
or t0, t0, t1
mttc0 t0, CP0_VPECONF0
@@ -280,8 +280,8 @@ LEAF(mips_cps_core_init)
mttc0 t0, CP0_TCHALT
/* Next VPE */
- addiu t5, t5, 1
- slt t0, t5, t7
+ addiu ta1, ta1, 1
+ slt t0, ta1, ta3
bnez t0, 1b
nop
@@ -310,7 +310,7 @@ LEAF(mips_cps_boot_vpes)
addu t0, t0, t1
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
- has_mt t6, 1f
+ has_mt ta2, 1f
li t9, 0
/* Find the number of VPEs present in the core */
@@ -334,13 +334,13 @@ LEAF(mips_cps_boot_vpes)
1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
li t1, VPEBOOTCFG_SIZE
mul v0, t9, t1
- lw t7, COREBOOTCFG_VPECONFIG(t0)
- addu v0, v0, t7
+ lw ta3, COREBOOTCFG_VPECONFIG(t0)
+ addu v0, v0, ta3
#ifdef CONFIG_MIPS_MT
/* If the core doesn't support MT then return */
- bnez t6, 1f
+ bnez ta2, 1f
nop
jr ra
nop
@@ -360,12 +360,12 @@ LEAF(mips_cps_boot_vpes)
ehb
/* Loop through each VPE */
- lw t6, COREBOOTCFG_VPEMASK(t0)
- move t8, t6
- li t5, 0
+ lw ta2, COREBOOTCFG_VPEMASK(t0)
+ move t8, ta2
+ li ta1, 0
/* Check whether the VPE should be running. If not, skip it */
-1: andi t0, t6, 1
+1: andi t0, ta2, 1
beqz t0, 2f
nop
@@ -373,7 +373,7 @@ LEAF(mips_cps_boot_vpes)
mfc0 t0, CP0_VPECONTROL
ori t0, t0, VPECONTROL_TARGTC
xori t0, t0, VPECONTROL_TARGTC
- or t0, t0, t5
+ or t0, t0, ta1
mtc0 t0, CP0_VPECONTROL
ehb
@@ -384,8 +384,8 @@ LEAF(mips_cps_boot_vpes)
/* Calculate a pointer to the VPEs struct vpe_boot_config */
li t0, VPEBOOTCFG_SIZE
- mul t0, t0, t5
- addu t0, t0, t7
+ mul t0, t0, ta1
+ addu t0, t0, ta3
/* Set the TC restart PC */
lw t1, VPEBOOTCFG_PC(t0)
@@ -423,9 +423,9 @@ LEAF(mips_cps_boot_vpes)
mttc0 t0, CP0_VPECONF0
/* Next VPE */
-2: srl t6, t6, 1
- addiu t5, t5, 1
- bnez t6, 1b
+2: srl ta2, ta2, 1
+ addiu ta1, ta1, 1
+ bnez ta2, 1b
nop
/* Leave VPE configuration state */
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/7] MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0
so 64-bit kernels can be supported.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 21f714a81ebd..2f95568e0da5 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -107,7 +107,7 @@ not_nmi:
mul t1, t1, t0
mul t1, t1, t2
- li a0, KSEG0
+ li a0, CKSEG0
add a1, a0, t1
1: cache Index_Store_Tag_I, 0(a0)
add a0, a0, t0
@@ -134,7 +134,7 @@ icache_done:
mul t1, t1, t0
mul t1, t1, t2
- li a0, KSEG0
+ li a0, CKSEG0
addu a1, a0, t1
subu a1, a1, t0
1: cache Index_Store_Tag_D, 0(a0)
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/7] MIPS: kernel: cps-vec: Replace KSEG0 with CKSEG0
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0
so 64-bit kernels can be supported.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 21f714a81ebd..2f95568e0da5 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -107,7 +107,7 @@ not_nmi:
mul t1, t1, t0
mul t1, t1, t2
- li a0, KSEG0
+ li a0, CKSEG0
add a1, a0, t1
1: cache Index_Store_Tag_I, 0(a0)
add a0, a0, t0
@@ -134,7 +134,7 @@ icache_done:
mul t1, t1, t0
mul t1, t1, t2
- li a0, KSEG0
+ li a0, CKSEG0
addu a1, a0, t1
subu a1, a1, t0
1: cache Index_Store_Tag_D, 0(a0)
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 6/7] MIPS: kernel: cps-vec: Use macros for various arithmetics and memory operations
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
Replace lw/sw and various arithmetic instructions with macros so the
code can work on 64-bit kernels as well.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 2f95568e0da5..1b6ca634e646 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -108,9 +108,9 @@ not_nmi:
mul t1, t1, t2
li a0, CKSEG0
- add a1, a0, t1
+ PTR_ADD a1, a0, t1
1: cache Index_Store_Tag_I, 0(a0)
- add a0, a0, t0
+ PTR_ADD a0, a0, t0
bne a0, a1, 1b
nop
icache_done:
@@ -135,11 +135,11 @@ icache_done:
mul t1, t1, t2
li a0, CKSEG0
- addu a1, a0, t1
- subu a1, a1, t0
+ PTR_ADDU a1, a0, t1
+ PTR_SUBU a1, a1, t0
1: cache Index_Store_Tag_D, 0(a0)
bne a0, a1, 1b
- add a0, a0, t0
+ PTR_ADD a0, a0, t0
dcache_done:
/* Set Kseg0 CCA to that in s0 */
@@ -152,7 +152,7 @@ dcache_done:
/* Enter the coherent domain */
li t0, 0xff
- sw t0, GCR_CL_COHERENCE_OFS(v1)
+ PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
ehb
/* Jump to kseg0 */
@@ -178,9 +178,9 @@ dcache_done:
nop
/* Off we go! */
- lw t1, VPEBOOTCFG_PC(v0)
- lw gp, VPEBOOTCFG_GP(v0)
- lw sp, VPEBOOTCFG_SP(v0)
+ PTR_L t1, VPEBOOTCFG_PC(v0)
+ PTR_L gp, VPEBOOTCFG_GP(v0)
+ PTR_L sp, VPEBOOTCFG_SP(v0)
jr t1
nop
END(mips_cps_core_entry)
@@ -299,15 +299,15 @@ LEAF(mips_cps_core_init)
LEAF(mips_cps_boot_vpes)
/* Retrieve CM base address */
PTR_LA t0, mips_cm_base
- lw t0, 0(t0)
+ PTR_L t0, 0(t0)
/* Calculate a pointer to this cores struct core_boot_config */
- lw t0, GCR_CL_ID_OFS(t0)
+ PTR_L t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
PTR_LA t1, mips_cps_core_bootcfg
- lw t1, 0(t1)
- addu t0, t0, t1
+ PTR_L t1, 0(t1)
+ PTR_ADDU t0, t0, t1
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
has_mt ta2, 1f
@@ -334,8 +334,8 @@ LEAF(mips_cps_boot_vpes)
1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
li t1, VPEBOOTCFG_SIZE
mul v0, t9, t1
- lw ta3, COREBOOTCFG_VPECONFIG(t0)
- addu v0, v0, ta3
+ PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
+ PTR_ADDU v0, v0, ta3
#ifdef CONFIG_MIPS_MT
@@ -360,7 +360,7 @@ LEAF(mips_cps_boot_vpes)
ehb
/* Loop through each VPE */
- lw ta2, COREBOOTCFG_VPEMASK(t0)
+ PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
move t8, ta2
li ta1, 0
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 6/7] MIPS: kernel: cps-vec: Use macros for various arithmetics and memory operations
@ 2015-07-01 8:13 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:13 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
Replace lw/sw and various arithmetic instructions with macros so the
code can work on 64-bit kernels as well.
Cc: <stable@vger.kernel.org> # 3.16+
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/kernel/cps-vec.S | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 2f95568e0da5..1b6ca634e646 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -108,9 +108,9 @@ not_nmi:
mul t1, t1, t2
li a0, CKSEG0
- add a1, a0, t1
+ PTR_ADD a1, a0, t1
1: cache Index_Store_Tag_I, 0(a0)
- add a0, a0, t0
+ PTR_ADD a0, a0, t0
bne a0, a1, 1b
nop
icache_done:
@@ -135,11 +135,11 @@ icache_done:
mul t1, t1, t2
li a0, CKSEG0
- addu a1, a0, t1
- subu a1, a1, t0
+ PTR_ADDU a1, a0, t1
+ PTR_SUBU a1, a1, t0
1: cache Index_Store_Tag_D, 0(a0)
bne a0, a1, 1b
- add a0, a0, t0
+ PTR_ADD a0, a0, t0
dcache_done:
/* Set Kseg0 CCA to that in s0 */
@@ -152,7 +152,7 @@ dcache_done:
/* Enter the coherent domain */
li t0, 0xff
- sw t0, GCR_CL_COHERENCE_OFS(v1)
+ PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
ehb
/* Jump to kseg0 */
@@ -178,9 +178,9 @@ dcache_done:
nop
/* Off we go! */
- lw t1, VPEBOOTCFG_PC(v0)
- lw gp, VPEBOOTCFG_GP(v0)
- lw sp, VPEBOOTCFG_SP(v0)
+ PTR_L t1, VPEBOOTCFG_PC(v0)
+ PTR_L gp, VPEBOOTCFG_GP(v0)
+ PTR_L sp, VPEBOOTCFG_SP(v0)
jr t1
nop
END(mips_cps_core_entry)
@@ -299,15 +299,15 @@ LEAF(mips_cps_core_init)
LEAF(mips_cps_boot_vpes)
/* Retrieve CM base address */
PTR_LA t0, mips_cm_base
- lw t0, 0(t0)
+ PTR_L t0, 0(t0)
/* Calculate a pointer to this cores struct core_boot_config */
- lw t0, GCR_CL_ID_OFS(t0)
+ PTR_L t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
PTR_LA t1, mips_cps_core_bootcfg
- lw t1, 0(t1)
- addu t0, t0, t1
+ PTR_L t1, 0(t1)
+ PTR_ADDU t0, t0, t1
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
has_mt ta2, 1f
@@ -334,8 +334,8 @@ LEAF(mips_cps_boot_vpes)
1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
li t1, VPEBOOTCFG_SIZE
mul v0, t9, t1
- lw ta3, COREBOOTCFG_VPECONFIG(t0)
- addu v0, v0, ta3
+ PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
+ PTR_ADDU v0, v0, ta3
#ifdef CONFIG_MIPS_MT
@@ -360,7 +360,7 @@ LEAF(mips_cps_boot_vpes)
ehb
/* Loop through each VPE */
- lw ta2, COREBOOTCFG_VPEMASK(t0)
+ PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
move t8, ta2
li ta1, 0
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 6/7] MIPS: kernel: cps-vec: Use macros for various arithmetics and memory operations
@ 2015-07-14 12:40 ` Paul Burton
0 siblings, 0 replies; 20+ messages in thread
From: Paul Burton @ 2015-07-14 12:40 UTC (permalink / raw)
To: Markos Chandras; +Cc: linux-mips, stable
On Wed, Jul 01, 2015 at 09:13:33AM +0100, Markos Chandras wrote:
> Replace lw/sw and various arithmetic instructions with macros so the
> code can work on 64-bit kernels as well.
>
> Cc: <stable@vger.kernel.org> # 3.16+
> Reviewed-by: Paul Burton <paul.burton@imgtec.com>
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> ---
> arch/mips/kernel/cps-vec.S | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
> index 2f95568e0da5..1b6ca634e646 100644
> --- a/arch/mips/kernel/cps-vec.S
> +++ b/arch/mips/kernel/cps-vec.S
> @@ -108,9 +108,9 @@ not_nmi:
> mul t1, t1, t2
>
> li a0, CKSEG0
> - add a1, a0, t1
> + PTR_ADD a1, a0, t1
> 1: cache Index_Store_Tag_I, 0(a0)
> - add a0, a0, t0
> + PTR_ADD a0, a0, t0
> bne a0, a1, 1b
> nop
> icache_done:
> @@ -135,11 +135,11 @@ icache_done:
> mul t1, t1, t2
>
> li a0, CKSEG0
> - addu a1, a0, t1
> - subu a1, a1, t0
> + PTR_ADDU a1, a0, t1
> + PTR_SUBU a1, a1, t0
> 1: cache Index_Store_Tag_D, 0(a0)
> bne a0, a1, 1b
> - add a0, a0, t0
> + PTR_ADD a0, a0, t0
> dcache_done:
>
> /* Set Kseg0 CCA to that in s0 */
> @@ -152,7 +152,7 @@ dcache_done:
>
> /* Enter the coherent domain */
> li t0, 0xff
> - sw t0, GCR_CL_COHERENCE_OFS(v1)
> + PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
Hi Markos,
I don't believe this is correct where accessing GCRs. Since you've
pushed elsewhere to perform 32 bit accesses when running a 32 bit kernel
on a MIPS64 core with CM3, can we just keep doing 32 bit accesses here?
> ehb
>
> /* Jump to kseg0 */
> @@ -178,9 +178,9 @@ dcache_done:
> nop
>
> /* Off we go! */
> - lw t1, VPEBOOTCFG_PC(v0)
> - lw gp, VPEBOOTCFG_GP(v0)
> - lw sp, VPEBOOTCFG_SP(v0)
> + PTR_L t1, VPEBOOTCFG_PC(v0)
> + PTR_L gp, VPEBOOTCFG_GP(v0)
> + PTR_L sp, VPEBOOTCFG_SP(v0)
> jr t1
> nop
> END(mips_cps_core_entry)
> @@ -299,15 +299,15 @@ LEAF(mips_cps_core_init)
> LEAF(mips_cps_boot_vpes)
> /* Retrieve CM base address */
> PTR_LA t0, mips_cm_base
> - lw t0, 0(t0)
> + PTR_L t0, 0(t0)
>
> /* Calculate a pointer to this cores struct core_boot_config */
> - lw t0, GCR_CL_ID_OFS(t0)
> + PTR_L t0, GCR_CL_ID_OFS(t0)
Ditto here.
Thanks,
Paul
> li t1, COREBOOTCFG_SIZE
> mul t0, t0, t1
> PTR_LA t1, mips_cps_core_bootcfg
> - lw t1, 0(t1)
> - addu t0, t0, t1
> + PTR_L t1, 0(t1)
> + PTR_ADDU t0, t0, t1
>
> /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
> has_mt ta2, 1f
> @@ -334,8 +334,8 @@ LEAF(mips_cps_boot_vpes)
> 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
> li t1, VPEBOOTCFG_SIZE
> mul v0, t9, t1
> - lw ta3, COREBOOTCFG_VPECONFIG(t0)
> - addu v0, v0, ta3
> + PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
> + PTR_ADDU v0, v0, ta3
>
> #ifdef CONFIG_MIPS_MT
>
> @@ -360,7 +360,7 @@ LEAF(mips_cps_boot_vpes)
> ehb
>
> /* Loop through each VPE */
> - lw ta2, COREBOOTCFG_VPEMASK(t0)
> + PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
> move t8, ta2
> li ta1, 0
>
> --
> 2.4.5
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 6/7] MIPS: kernel: cps-vec: Use macros for various arithmetics and memory operations
@ 2015-07-14 12:40 ` Paul Burton
0 siblings, 0 replies; 20+ messages in thread
From: Paul Burton @ 2015-07-14 12:40 UTC (permalink / raw)
To: Markos Chandras; +Cc: linux-mips, stable
On Wed, Jul 01, 2015 at 09:13:33AM +0100, Markos Chandras wrote:
> Replace lw/sw and various arithmetic instructions with macros so the
> code can work on 64-bit kernels as well.
>
> Cc: <stable@vger.kernel.org> # 3.16+
> Reviewed-by: Paul Burton <paul.burton@imgtec.com>
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> ---
> arch/mips/kernel/cps-vec.S | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
> index 2f95568e0da5..1b6ca634e646 100644
> --- a/arch/mips/kernel/cps-vec.S
> +++ b/arch/mips/kernel/cps-vec.S
> @@ -108,9 +108,9 @@ not_nmi:
> mul t1, t1, t2
>
> li a0, CKSEG0
> - add a1, a0, t1
> + PTR_ADD a1, a0, t1
> 1: cache Index_Store_Tag_I, 0(a0)
> - add a0, a0, t0
> + PTR_ADD a0, a0, t0
> bne a0, a1, 1b
> nop
> icache_done:
> @@ -135,11 +135,11 @@ icache_done:
> mul t1, t1, t2
>
> li a0, CKSEG0
> - addu a1, a0, t1
> - subu a1, a1, t0
> + PTR_ADDU a1, a0, t1
> + PTR_SUBU a1, a1, t0
> 1: cache Index_Store_Tag_D, 0(a0)
> bne a0, a1, 1b
> - add a0, a0, t0
> + PTR_ADD a0, a0, t0
> dcache_done:
>
> /* Set Kseg0 CCA to that in s0 */
> @@ -152,7 +152,7 @@ dcache_done:
>
> /* Enter the coherent domain */
> li t0, 0xff
> - sw t0, GCR_CL_COHERENCE_OFS(v1)
> + PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
Hi Markos,
I don't believe this is correct where accessing GCRs. Since you've
pushed elsewhere to perform 32 bit accesses when running a 32 bit kernel
on a MIPS64 core with CM3, can we just keep doing 32 bit accesses here?
> ehb
>
> /* Jump to kseg0 */
> @@ -178,9 +178,9 @@ dcache_done:
> nop
>
> /* Off we go! */
> - lw t1, VPEBOOTCFG_PC(v0)
> - lw gp, VPEBOOTCFG_GP(v0)
> - lw sp, VPEBOOTCFG_SP(v0)
> + PTR_L t1, VPEBOOTCFG_PC(v0)
> + PTR_L gp, VPEBOOTCFG_GP(v0)
> + PTR_L sp, VPEBOOTCFG_SP(v0)
> jr t1
> nop
> END(mips_cps_core_entry)
> @@ -299,15 +299,15 @@ LEAF(mips_cps_core_init)
> LEAF(mips_cps_boot_vpes)
> /* Retrieve CM base address */
> PTR_LA t0, mips_cm_base
> - lw t0, 0(t0)
> + PTR_L t0, 0(t0)
>
> /* Calculate a pointer to this cores struct core_boot_config */
> - lw t0, GCR_CL_ID_OFS(t0)
> + PTR_L t0, GCR_CL_ID_OFS(t0)
Ditto here.
Thanks,
Paul
> li t1, COREBOOTCFG_SIZE
> mul t0, t0, t1
> PTR_LA t1, mips_cps_core_bootcfg
> - lw t1, 0(t1)
> - addu t0, t0, t1
> + PTR_L t1, 0(t1)
> + PTR_ADDU t0, t0, t1
>
> /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
> has_mt ta2, 1f
> @@ -334,8 +334,8 @@ LEAF(mips_cps_boot_vpes)
> 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
> li t1, VPEBOOTCFG_SIZE
> mul v0, t9, t1
> - lw ta3, COREBOOTCFG_VPECONFIG(t0)
> - addu v0, v0, ta3
> + PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
> + PTR_ADDU v0, v0, ta3
>
> #ifdef CONFIG_MIPS_MT
>
> @@ -360,7 +360,7 @@ LEAF(mips_cps_boot_vpes)
> ehb
>
> /* Loop through each VPE */
> - lw ta2, COREBOOTCFG_VPEMASK(t0)
> + PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
> move t8, ta2
> li ta1, 0
>
> --
> 2.4.5
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 6/7] MIPS: kernel: cps-vec: Use macros for various arithmetics and memory operations
@ 2015-07-14 13:07 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-14 13:07 UTC (permalink / raw)
To: Paul Burton; +Cc: linux-mips, stable
On 07/14/2015 01:40 PM, Paul Burton wrote:
>> @@ -152,7 +152,7 @@ dcache_done:
>>
>> /* Enter the coherent domain */
>> li t0, 0xff
>> - sw t0, GCR_CL_COHERENCE_OFS(v1)
>> + PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
>
> Hi Markos,
>
> I don't believe this is correct where accessing GCRs. Since you've
> pushed elsewhere to perform 32 bit accesses when running a 32 bit kernel
> on a MIPS64 core with CM3, can we just keep doing 32 bit accesses here?
>
Hi Paul,
Yes. This patch is already upstream though. I will wait for the
'mips_cm_is64' to make it upstream as well and then I will submit a fix
for this one. It should not break anything at the moment. Thanks
--
markos
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 6/7] MIPS: kernel: cps-vec: Use macros for various arithmetics and memory operations
@ 2015-07-14 13:07 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-14 13:07 UTC (permalink / raw)
To: Paul Burton; +Cc: linux-mips, stable
On 07/14/2015 01:40 PM, Paul Burton wrote:
>> @@ -152,7 +152,7 @@ dcache_done:
>>
>> /* Enter the coherent domain */
>> li t0, 0xff
>> - sw t0, GCR_CL_COHERENCE_OFS(v1)
>> + PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
>
> Hi Markos,
>
> I don't believe this is correct where accessing GCRs. Since you've
> pushed elsewhere to perform 32 bit accesses when running a 32 bit kernel
> on a MIPS64 core with CM3, can we just keep doing 32 bit accesses here?
>
Hi Paul,
Yes. This patch is already upstream though. I will wait for the
'mips_cm_is64' to make it upstream as well and then I will submit a fix
for this one. It should not break anything at the moment. Thanks
--
markos
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 7/7] Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit"
@ 2015-07-01 8:31 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:31 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
This reverts commit 6ca716f2e5571d25a3899c6c5c91ff72ea6d6f5e.
SMP/CPS is now supported on 64bit cores.
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f5016656494f..003cf61080b1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2220,7 +2220,7 @@ config MIPS_CMP
config MIPS_CPS
bool "MIPS Coherent Processing System support"
- depends on SYS_SUPPORTS_MIPS_CPS && !64BIT
+ depends on SYS_SUPPORTS_MIPS_CPS
select MIPS_CM
select MIPS_CPC
select MIPS_CPS_PM if HOTPLUG_CPU
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 7/7] Revert "MIPS: Kconfig: Disable SMP/CPS for 64-bit"
@ 2015-07-01 8:31 ` Markos Chandras
0 siblings, 0 replies; 20+ messages in thread
From: Markos Chandras @ 2015-07-01 8:31 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras, stable
This reverts commit 6ca716f2e5571d25a3899c6c5c91ff72ea6d6f5e.
SMP/CPS is now supported on 64bit cores.
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f5016656494f..003cf61080b1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2220,7 +2220,7 @@ config MIPS_CMP
config MIPS_CPS
bool "MIPS Coherent Processing System support"
- depends on SYS_SUPPORTS_MIPS_CPS && !64BIT
+ depends on SYS_SUPPORTS_MIPS_CPS
select MIPS_CM
select MIPS_CPC
select MIPS_CPS_PM if HOTPLUG_CPU
--
2.4.5
^ permalink raw reply related [flat|nested] 20+ messages in thread