[U-Boot] [PATCHv4 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

[Dinh Nguyen <dinguyen@opensource.altera.com>]

On 07/20/2015 02:40 PM, Marek Vasut wrote:
> On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
> [...]
>>>>> Hi,
>>>>>
>>>>> yeah, I have some insane amount of cleanup patches and fixes already. I
>>>>> will post them once I'm done. What I am sorely missing is the UniPHY
>>>>> register interface documentation, it looks like that is not public, so
>>>>> I don't exactly know if what sequencer.c does is really correct.
>>>>> Sometimes I have serious doubts about that too . Can you give me the
>>>>> documentation please ?
>>>>
>>>> Have you seen this link[1]?
>>>
>>> Yes, but that is by far not all of the registers used in the sequencer.c,
>>> is it ?
>>
>> Looks like it's in the entire emi.pdf file[1]. Please look at volume 3,
>> or page 531 of 895. The section for the UniPHY.
> 
> I extracted all the possible addresses used in the sequencer while cleaning
> it up, they're below. I cannot find these in any documentation. I checked the
> EMI RM, sure, but there seems to be many more registers all around the place
> than what are described in the EMI RM. Any ideas please ? Maybe this is not
> even the UniPHY anymore ?
> 

I'll try to get those questions answered for you shortly.

BTW, I tested out our your branch, but I think I'm missing a step as
where to put the SPL DTB?


U-Boot SPL 2015.07-rc3-00100-ga2e2da6 (Jul 21 2015 - 17:15:54)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Missing DTB
### ERROR ### Please RESET the board ###

Thanks,
Dinh