[PATCH 0/4] Improvements on exynos7 clock

[PATCH 0/4] Improvements on exynos7 clock

[Alim Akhtar]

This patch series are minor improvement over the current
exynos7 clock file. This fix some bugs and update the clock
bits as per latest user manual.

This serise is tested on exynos7-espresso board.

Alim Akhtar (4):
  clk: samsung: exynos7: Update CMU TOPC block clock
  clk: samsung: exynos7: Update CMU TOP1 block
  clk: samsung: exynos7: Correct nr_clk_ids for fsys0
  clk: samsung: exynos7: correct nr_clk_ids for fsys1

 drivers/clk/samsung/clk-exynos7.c |   49 +++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 21 deletions(-)

-- 
1.7.10.4

[PATCH 1/4] clk: samsung: exynos7: Update CMU TOPC block clock

[Alim Akhtar]

This patch fixes some of the bit field and
update the TOPC block clock as per the latest UM.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c |   15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 03d36e8..cbf1bd2 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -87,6 +87,7 @@ static unsigned long topc_clk_regs[] __initdata = {
 	DIV_TOPC0,
 	DIV_TOPC1,
 	DIV_TOPC3,
+	ENABLE_ACLK_TOPC1,
 };
 
 static struct samsung_mux_clock topc_mux_clks[] __initdata = {
@@ -104,9 +105,9 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
 	MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
 		MUX_SEL_TOPC0, 28, 1),
 
+	MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
 	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
 		MUX_SEL_TOPC1, 16, 1),
-	MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
 
 	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
 
@@ -116,7 +117,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
 
 static struct samsung_div_clock topc_div_clks[] __initdata = {
 	DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
-		DIV_TOPC0, 4, 4),
+		DIV_TOPC0, 4, 5),
 
 	DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
 		DIV_TOPC1, 20, 4),
@@ -124,15 +125,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
 		DIV_TOPC1, 24, 4),
 
 	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
-		DIV_TOPC3, 0, 3),
+		DIV_TOPC3, 0, 4),
 	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
-		DIV_TOPC3, 8, 3),
+		DIV_TOPC3, 8, 4),
 	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
-		DIV_TOPC3, 12, 3),
+		DIV_TOPC3, 12, 4),
 	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
-		DIV_TOPC3, 16, 3),
+		DIV_TOPC3, 16, 4),
 	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
-		DIV_TOPC3, 28, 3),
+		DIV_TOPC3, 28, 4),
 };
 
 static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
-- 
1.7.10.4

[PATCH 2/4] clk: samsung: exynos7: Update CMU TOP1 block

[Alim Akhtar]

This updates CMU TOP1 block clock as per latest UM.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c |   24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index cbf1bd2..d6c4548 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -368,12 +368,15 @@ CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
 #define MUX_SEL_TOP13			0x020C
 #define MUX_SEL_TOP1_FSYS0		0x0224
 #define MUX_SEL_TOP1_FSYS1		0x0228
+#define MUX_SEL_TOP1_FSYS11		0x022C
 #define DIV_TOP13			0x060C
 #define DIV_TOP1_FSYS0			0x0624
 #define DIV_TOP1_FSYS1			0x0628
+#define DIV_TOP1_FSYS11			0x062C
 #define ENABLE_ACLK_TOP13		0x080C
 #define ENABLE_SCLK_TOP1_FSYS0		0x0A24
 #define ENABLE_SCLK_TOP1_FSYS1		0x0A28
+#define ENABLE_SCLK_TOP1_FSYS11		0x0A2C
 
 /* List of parent clocks for Muxes in CMU_TOP1 */
 PNAME(mout_top1_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
@@ -400,12 +403,15 @@ static unsigned long top1_clk_regs[] __initdata = {
 	MUX_SEL_TOP13,
 	MUX_SEL_TOP1_FSYS0,
 	MUX_SEL_TOP1_FSYS1,
+	MUX_SEL_TOP1_FSYS11,
 	DIV_TOP13,
 	DIV_TOP1_FSYS0,
 	DIV_TOP1_FSYS1,
+	DIV_TOP1_FSYS11,
 	ENABLE_ACLK_TOP13,
 	ENABLE_SCLK_TOP1_FSYS0,
 	ENABLE_SCLK_TOP1_FSYS1,
+	ENABLE_SCLK_TOP1_FSYS11,
 };
 
 static struct samsung_mux_clock top1_mux_clks[] __initdata = {
@@ -428,12 +434,12 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
 	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
 	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
 
-	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
 	MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
 		MUX_SEL_TOP1_FSYS0, 28, 2),
 
-	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
-	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
+	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
+	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
 };
 
 static struct samsung_div_clock top1_div_clks[] __initdata = {
@@ -443,26 +449,26 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 		DIV_TOP13, 28, 4),
 
 	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
-		DIV_TOP1_FSYS0, 24, 4),
+		DIV_TOP1_FSYS0, 16, 10),
 	DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
 		DIV_TOP1_FSYS0, 28, 4),
 
 	DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
-		DIV_TOP1_FSYS1, 24, 4),
+		DIV_TOP1_FSYS11, 0, 10),
 	DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
-		DIV_TOP1_FSYS1, 28, 4),
+		DIV_TOP1_FSYS11, 12, 10),
 };
 
 static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
-		ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+		ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
 	GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
 		ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
 
 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
-		ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
+		ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
-		ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
+		ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
-- 
1.7.10.4

[PATCH 3/4] clk: samsung: exynos7: Correct nr_clk_ids for fsys0

[Alim Akhtar]

This patch correct the nr_clk_ids for fsys0 block
which is wrongly set to TOP1 clk numbers.
This also adjust the a gate clock order.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index d6c4548..2799568 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -849,13 +849,13 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
-	GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
-		"mout_aclk_fsys0_200_user",
-		ENABLE_ACLK_FSYS00, 19, 0, 0),
 	GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
 			ENABLE_ACLK_FSYS00, 3, 0, 0),
 	GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
 			ENABLE_ACLK_FSYS00, 4, 0, 0),
+	GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
+		"mout_aclk_fsys0_200_user",
+		ENABLE_ACLK_FSYS00, 19, 0, 0),
 
 	GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
 		ENABLE_ACLK_FSYS01, 29, 0, 0),
@@ -887,7 +887,7 @@ static struct samsung_cmu_info fsys0_cmu_info __initdata = {
 	.nr_mux_clks		= ARRAY_SIZE(fsys0_mux_clks),
 	.gate_clks		= fsys0_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(fsys0_gate_clks),
-	.nr_clk_ids		= TOP1_NR_CLK,
+	.nr_clk_ids		= FSYS0_NR_CLK,
 	.clk_regs		= fsys0_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(fsys0_clk_regs),
 };
-- 
1.7.10.4

[PATCH 4/4] clk: samsung: exynos7: correct nr_clk_ids for fsys1

[Alim Akhtar]

nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch correct the same.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 2799568..0d7bb7c 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -938,7 +938,7 @@ static struct samsung_cmu_info fsys1_cmu_info __initdata = {
 	.nr_mux_clks		= ARRAY_SIZE(fsys1_mux_clks),
 	.gate_clks		= fsys1_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
-	.nr_clk_ids		= TOP1_NR_CLK,
+	.nr_clk_ids		= FSYS1_NR_CLK,
 	.clk_regs		= fsys1_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),
 };
-- 
1.7.10.4

Re: [PATCH 1/4] clk: samsung: exynos7: Update CMU TOPC block clock

[Krzysztof Kozlowski]

On 24.08.2015 20:05, Alim Akhtar wrote:
> This patch fixes some of the bit field and
> update the TOPC block clock as per the latest UM.

Description is not entirely correct. The "ENABLE_ACLK_TOPC1" register
was present already both in driver and in first user manual. That means
it was just forgotten to be saved/restored during sleep. There is no
update for manual because manual did not change anything.

The same for widths of bit fields - the 0.00 manual specifies them as 4
bit wide. Where is the change from latest UM?

Please describe the change as it is - clock driver was bogus and has to
be fixed :) .

Best regards,
Krzysztof

> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c |   15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 03d36e8..cbf1bd2 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -87,6 +87,7 @@ static unsigned long topc_clk_regs[] __initdata = {
>  	DIV_TOPC0,
>  	DIV_TOPC1,
>  	DIV_TOPC3,
> +	ENABLE_ACLK_TOPC1,
>  };
>  
>  static struct samsung_mux_clock topc_mux_clks[] __initdata = {
> @@ -104,9 +105,9 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>  	MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
>  		MUX_SEL_TOPC0, 28, 1),
>  
> +	MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
>  	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
>  		MUX_SEL_TOPC1, 16, 1),
> -	MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
>  
>  	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
>  
> @@ -116,7 +117,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>  
>  static struct samsung_div_clock topc_div_clks[] __initdata = {
>  	DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
> -		DIV_TOPC0, 4, 4),
> +		DIV_TOPC0, 4, 5),
>  
>  	DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
>  		DIV_TOPC1, 20, 4),
> @@ -124,15 +125,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
>  		DIV_TOPC1, 24, 4),
>  
>  	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
> -		DIV_TOPC3, 0, 3),
> +		DIV_TOPC3, 0, 4),
>  	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
> -		DIV_TOPC3, 8, 3),
> +		DIV_TOPC3, 8, 4),
>  	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
> -		DIV_TOPC3, 12, 3),
> +		DIV_TOPC3, 12, 4),
>  	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
> -		DIV_TOPC3, 16, 3),
> +		DIV_TOPC3, 16, 4),
>  	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
> -		DIV_TOPC3, 28, 3),
> +		DIV_TOPC3, 28, 4),
>  };
>  
>  static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
> 

Re: [PATCH 2/4] clk: samsung: exynos7: Update CMU TOP1 block

[Krzysztof Kozlowski]

On 24.08.2015 20:05, Alim Akhtar wrote:
> This updates CMU TOP1 block clock as per latest UM.

I think description is not entirely correct. Some of the changes here
were present in the first manual. Please describe it more, what exactly
is being fixed and updated to latest UM.

Best regards,
Krzysztof

> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c |   24 +++++++++++++++---------
>  1 file changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index cbf1bd2..d6c4548 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -368,12 +368,15 @@ CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
>  #define MUX_SEL_TOP13			0x020C
>  #define MUX_SEL_TOP1_FSYS0		0x0224
>  #define MUX_SEL_TOP1_FSYS1		0x0228
> +#define MUX_SEL_TOP1_FSYS11		0x022C
>  #define DIV_TOP13			0x060C
>  #define DIV_TOP1_FSYS0			0x0624
>  #define DIV_TOP1_FSYS1			0x0628
> +#define DIV_TOP1_FSYS11			0x062C
>  #define ENABLE_ACLK_TOP13		0x080C
>  #define ENABLE_SCLK_TOP1_FSYS0		0x0A24
>  #define ENABLE_SCLK_TOP1_FSYS1		0x0A28
> +#define ENABLE_SCLK_TOP1_FSYS11		0x0A2C
>  
>  /* List of parent clocks for Muxes in CMU_TOP1 */
>  PNAME(mout_top1_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
> @@ -400,12 +403,15 @@ static unsigned long top1_clk_regs[] __initdata = {
>  	MUX_SEL_TOP13,
>  	MUX_SEL_TOP1_FSYS0,
>  	MUX_SEL_TOP1_FSYS1,
> +	MUX_SEL_TOP1_FSYS11,
>  	DIV_TOP13,
>  	DIV_TOP1_FSYS0,
>  	DIV_TOP1_FSYS1,
> +	DIV_TOP1_FSYS11,
>  	ENABLE_ACLK_TOP13,
>  	ENABLE_SCLK_TOP1_FSYS0,
>  	ENABLE_SCLK_TOP1_FSYS1,
> +	ENABLE_SCLK_TOP1_FSYS11,
>  };
>  
>  static struct samsung_mux_clock top1_mux_clks[] __initdata = {
> @@ -428,12 +434,12 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
>  	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
>  	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
>  
> -	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
> +	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
>  	MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
>  		MUX_SEL_TOP1_FSYS0, 28, 2),
>  
> -	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
> -	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
> +	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
> +	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
>  };
>  
>  static struct samsung_div_clock top1_div_clks[] __initdata = {
> @@ -443,26 +449,26 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
>  		DIV_TOP13, 28, 4),
>  
>  	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
> -		DIV_TOP1_FSYS0, 24, 4),
> +		DIV_TOP1_FSYS0, 16, 10),
>  	DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
>  		DIV_TOP1_FSYS0, 28, 4),
>  
>  	DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
> -		DIV_TOP1_FSYS1, 24, 4),
> +		DIV_TOP1_FSYS11, 0, 10),
>  	DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
> -		DIV_TOP1_FSYS1, 28, 4),
> +		DIV_TOP1_FSYS11, 12, 10),
>  };
>  
>  static struct samsung_gate_clock top1_gate_clks[] __initdata = {
>  	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
> -		ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
> +		ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
>  	GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
>  		ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
>  
>  	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
> -		ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
> +		ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
>  	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
> -		ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
> +		ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
>  };
>  
>  static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
> 

Re: [PATCH 3/4] clk: samsung: exynos7: Correct nr_clk_ids for fsys0

[Krzysztof Kozlowski]

On 24.08.2015 20:05, Alim Akhtar wrote:
> This patch correct the nr_clk_ids for fsys0 block
s/correct/corrects/

> which is wrongly set to TOP1 clk numbers.
> This also adjust the a gate clock order.
s/adjust the a/adjusts the/

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

Re: [PATCH 4/4] clk: samsung: exynos7: correct nr_clk_ids for fsys1

[Krzysztof Kozlowski]

On 24.08.2015 20:05, Alim Akhtar wrote:
> nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
> this patch correct the same.
s/correct the same/corrects it/

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof


> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 2799568..0d7bb7c 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -938,7 +938,7 @@ static struct samsung_cmu_info fsys1_cmu_info __initdata = {
>  	.nr_mux_clks		= ARRAY_SIZE(fsys1_mux_clks),
>  	.gate_clks		= fsys1_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
> -	.nr_clk_ids		= TOP1_NR_CLK,
> +	.nr_clk_ids		= FSYS1_NR_CLK,
>  	.clk_regs		= fsys1_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),
>  };
> 

Re: [PATCH 1/4] clk: samsung: exynos7: Update CMU TOPC block clock

[Alim Akhtar]

Hello Krzysztof,

On Tue, Aug 25, 2015 at 12:32 PM, Krzysztof Kozlowski
<k.kozlowski@samsung.com> wrote:
> On 24.08.2015 20:05, Alim Akhtar wrote:
>> This patch fixes some of the bit field and
>> update the TOPC block clock as per the latest UM.
>
> Description is not entirely correct. The "ENABLE_ACLK_TOPC1" register
> was present already both in driver and in first user manual. That means
> it was just forgotten to be saved/restored during sleep. There is no
> update for manual because manual did not change anything.
>
> The same for widths of bit fields - the 0.00 manual specifies them as 4
> bit wide. Where is the change from latest UM?
>
Thanks for your review, will update the commit message and remove
ENABLE_ACLK_TOPC1 for now.
> Please describe the change as it is - clock driver was bogus and has to
> be fixed :) .
>

> Best regards,
> Krzysztof
>
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos7.c |   15 ++++++++-------
>>  1 file changed, 8 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index 03d36e8..cbf1bd2 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -87,6 +87,7 @@ static unsigned long topc_clk_regs[] __initdata = {
>>       DIV_TOPC0,
>>       DIV_TOPC1,
>>       DIV_TOPC3,
>> +     ENABLE_ACLK_TOPC1,
>>  };
>>
>>  static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>> @@ -104,9 +105,9 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>>       MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
>>               MUX_SEL_TOPC0, 28, 1),
>>
>> +     MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
>>       MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
>>               MUX_SEL_TOPC1, 16, 1),
>> -     MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
>>
>>       MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
>>
>> @@ -116,7 +117,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>>
>>  static struct samsung_div_clock topc_div_clks[] __initdata = {
>>       DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
>> -             DIV_TOPC0, 4, 4),
>> +             DIV_TOPC0, 4, 5),
>>
>>       DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
>>               DIV_TOPC1, 20, 4),
>> @@ -124,15 +125,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
>>               DIV_TOPC1, 24, 4),
>>
>>       DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
>> -             DIV_TOPC3, 0, 3),
>> +             DIV_TOPC3, 0, 4),
>>       DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
>> -             DIV_TOPC3, 8, 3),
>> +             DIV_TOPC3, 8, 4),
>>       DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
>> -             DIV_TOPC3, 12, 3),
>> +             DIV_TOPC3, 12, 4),
>>       DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
>> -             DIV_TOPC3, 16, 3),
>> +             DIV_TOPC3, 16, 4),
>>       DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
>> -             DIV_TOPC3, 28, 3),
>> +             DIV_TOPC3, 28, 4),
>>  };
>>
>>  static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
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-- 
Regards,
Alim

Re: [PATCH 2/4] clk: samsung: exynos7: Update CMU TOP1 block

[Alim Akhtar]

Hello Krzysztof,

On Tue, Aug 25, 2015 at 12:35 PM, Krzysztof Kozlowski
<k.kozlowski@samsung.com> wrote:
> On 24.08.2015 20:05, Alim Akhtar wrote:
>> This updates CMU TOP1 block clock as per latest UM.
>
> I think description is not entirely correct. Some of the changes here
> were present in the first manual. Please describe it more, what exactly
> is being fixed and updated to latest UM.
>
Ok, will add details and update the commit message.
> Best regards,
> Krzysztof
>
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos7.c |   24 +++++++++++++++---------
>>  1 file changed, 15 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index cbf1bd2..d6c4548 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -368,12 +368,15 @@ CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
>>  #define MUX_SEL_TOP13                        0x020C
>>  #define MUX_SEL_TOP1_FSYS0           0x0224
>>  #define MUX_SEL_TOP1_FSYS1           0x0228
>> +#define MUX_SEL_TOP1_FSYS11          0x022C
>>  #define DIV_TOP13                    0x060C
>>  #define DIV_TOP1_FSYS0                       0x0624
>>  #define DIV_TOP1_FSYS1                       0x0628
>> +#define DIV_TOP1_FSYS11                      0x062C
>>  #define ENABLE_ACLK_TOP13            0x080C
>>  #define ENABLE_SCLK_TOP1_FSYS0               0x0A24
>>  #define ENABLE_SCLK_TOP1_FSYS1               0x0A28
>> +#define ENABLE_SCLK_TOP1_FSYS11              0x0A2C
>>
>>  /* List of parent clocks for Muxes in CMU_TOP1 */
>>  PNAME(mout_top1_bus0_pll_p)  = { "fin_pll", "dout_sclk_bus0_pll" };
>> @@ -400,12 +403,15 @@ static unsigned long top1_clk_regs[] __initdata = {
>>       MUX_SEL_TOP13,
>>       MUX_SEL_TOP1_FSYS0,
>>       MUX_SEL_TOP1_FSYS1,
>> +     MUX_SEL_TOP1_FSYS11,
>>       DIV_TOP13,
>>       DIV_TOP1_FSYS0,
>>       DIV_TOP1_FSYS1,
>> +     DIV_TOP1_FSYS11,
>>       ENABLE_ACLK_TOP13,
>>       ENABLE_SCLK_TOP1_FSYS0,
>>       ENABLE_SCLK_TOP1_FSYS1,
>> +     ENABLE_SCLK_TOP1_FSYS11,
>>  };
>>
>>  static struct samsung_mux_clock top1_mux_clks[] __initdata = {
>> @@ -428,12 +434,12 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
>>       MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
>>       MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
>>
>> -     MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
>> +     MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
>>       MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
>>               MUX_SEL_TOP1_FSYS0, 28, 2),
>>
>> -     MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
>> -     MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
>> +     MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
>> +     MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
>>  };
>>
>>  static struct samsung_div_clock top1_div_clks[] __initdata = {
>> @@ -443,26 +449,26 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
>>               DIV_TOP13, 28, 4),
>>
>>       DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
>> -             DIV_TOP1_FSYS0, 24, 4),
>> +             DIV_TOP1_FSYS0, 16, 10),
>>       DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
>>               DIV_TOP1_FSYS0, 28, 4),
>>
>>       DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
>> -             DIV_TOP1_FSYS1, 24, 4),
>> +             DIV_TOP1_FSYS11, 0, 10),
>>       DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
>> -             DIV_TOP1_FSYS1, 28, 4),
>> +             DIV_TOP1_FSYS11, 12, 10),
>>  };
>>
>>  static struct samsung_gate_clock top1_gate_clks[] __initdata = {
>>       GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
>> -             ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
>> +             ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
>>       GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
>>               ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
>>
>>       GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
>> -             ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
>> +             ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
>>       GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
>> -             ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
>> +             ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
>>  };
>>
>>  static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
>>
>
> --
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-- 
Regards,
Alim

Re: [PATCH 3/4] clk: samsung: exynos7: Correct nr_clk_ids for fsys0

[Alim Akhtar]

Hello Krzysztof,

On Tue, Aug 25, 2015 at 12:46 PM, Krzysztof Kozlowski
<k.kozlowski@samsung.com> wrote:
> On 24.08.2015 20:05, Alim Akhtar wrote:
>> This patch correct the nr_clk_ids for fsys0 block
> s/correct/corrects/
>
>> which is wrongly set to TOP1 clk numbers.
>> This also adjust the a gate clock order.
> s/adjust the a/adjusts the/
>
will update
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
Thanks!

> Best regards,
> Krzysztof
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
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-- 
Regards,
Alim

Re: [PATCH 4/4] clk: samsung: exynos7: correct nr_clk_ids for fsys1

[Alim Akhtar]

Hello Krzysztof,

On Tue, Aug 25, 2015 at 12:48 PM, Krzysztof Kozlowski
<k.kozlowski@samsung.com> wrote:
> On 24.08.2015 20:05, Alim Akhtar wrote:
>> nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
>> this patch correct the same.
> s/correct the same/corrects it/
>
will update
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
Thanks!
> Best regards,
> Krzysztof
>
>
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos7.c |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index 2799568..0d7bb7c 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -938,7 +938,7 @@ static struct samsung_cmu_info fsys1_cmu_info __initdata = {
>>       .nr_mux_clks            = ARRAY_SIZE(fsys1_mux_clks),
>>       .gate_clks              = fsys1_gate_clks,
>>       .nr_gate_clks           = ARRAY_SIZE(fsys1_gate_clks),
>> -     .nr_clk_ids             = TOP1_NR_CLK,
>> +     .nr_clk_ids             = FSYS1_NR_CLK,
>>       .clk_regs               = fsys1_clk_regs,
>>       .nr_clk_regs            = ARRAY_SIZE(fsys1_clk_regs),
>>  };
>>
>
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-- 
Regards,
Alim