Re: [PATCH 0/8] RFC: more flexcan cleanups and SW FIFO IRQ offloading

[Marc Kleine-Budde <mkl@pengutronix.de>]

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On 09/03/2015 08:32 AM, David Jander wrote:
>>> this series adds a software FIFO implementation and switches
>>  > the flecan and at91 driver to it. It's intended for CAN cores
>>  > with a higher number of mailboxes.
>>
>> It is a bit difficult to understand the changed by looking at 20 patches, so 
>> I'm assuming this is the change where what the i.MX6 manuals calls the 
>> "Reception Queue" mode is enabled.

In the first series the "real" change happens at Patch 12/12. The
hardware FIFO which was handled in NAPI now it's handled in a hard IRQ
context. It's making use of the code introduced in patch 11/12.

>> I see "[PATCH 1/8]" renaming "FLEXCAN_MCR_BCC" to "FLEXCAN_MCR_IRMQ" and 
>> "[PATCH 2/8]" adding it to the MCR setting.

These are just preparation patches. But you're right, the MCR_IRMQ is
essential for software FIFO.

>> Use of the "Reception Queue" is documented in the i.MX6DQ manual in section 
>> "26.6.5 Matching Process" as:
>>
>>      By programming more than one MB with the same ID, received
>>      messages will be queued into the MBs. ARM can examine the
>>      Time Stamp field of the MBs to determine the order in which
>>      the messages arrived.
>>
>> Is the new code sorting the messages by using the timestamp, or have you
>> found another way to guarantee reception order?
> 
> Almost. Generic code in can/dev.c cannot know about special features like
> timestamps that some peripherals may provide.

Thanks to David explaining the algorithm.

The generic code is added in 5/8, the flexcan specific code is added in 7/8.

Regarding the time stamp feature. IIRC, the mailboxes in the AT91 have
timestamps, too. When the generic SW-FIFO code is stable and someone is
interested, sorting by timestamps can be added to the generic code base.

Marc

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