From: Tom Evans <tom_usenet@optusnet.com.au>
To: Marc Kleine-Budde <mkl@pengutronix.de>, David Jander <david@protonic.nl>
Cc: linux-can@vger.kernel.org, kernel@pengutronix.de
Subject: Re: [PATCH 0/8] RFC: more flexcan cleanups and SW FIFO IRQ offloading
Date: Thu, 3 Sep 2015 18:17:53 +1000 [thread overview]
Message-ID: <55E80231.30808@optusnet.com.au> (raw)
In-Reply-To: <55E7EF8D.306@pengutronix.de>
On 03/09/15 16:58, Marc Kleine-Budde wrote:
> On 09/03/2015 08:32 AM, David Jander wrote:
>>>> this series adds a software FIFO implementation and switches
Thank you both for explaining that.
It seems fairly bulletproof as long as it doesn't overflow. There are 64
buffers, so 32 in the first half, so that handles a 1.5ms interrupt latency.
A shame Freescale didn't think of that method instead of requiring the driver
run quicksort somewhere.
> In an atomic operation, the MB's that have been served are
> now disabled.
That's the sort of tricky operation that exposes nasty silicon bugs. I'd
suggest that this mode be made easy to turn off in case some chip variant has
a problem like htis.
This feature looks to be enabled as a "QUIRK" of the CPU.
In an old generation kernel this might be optionally enabled in the .config
file, as NAPI is in the 2.6.35 FEC drivers I'm stuck with using at the moment
on the i.MX53. In the current kernel, could this mode of operation (and/or
hardware FIFO using NAPI) be made configurable in the Device Tree instead?
Tom
next prev parent reply other threads:[~2015-09-03 8:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-01 10:31 [PATCH 0/8] RFC: more flexcan cleanups and SW FIFO IRQ offloading Marc Kleine-Budde
2015-09-01 10:31 ` [PATCH 1/8] can: flexcan: add missing register definitions Marc Kleine-Budde
2015-09-01 10:31 ` [PATCH 2/8] can: flexcan: activate individual RX masking and initialize reg_rximr Marc Kleine-Budde
2015-09-01 10:31 ` [PATCH 3/8] can: flexcan: add quirk FLEXCAN_QUIRK_ENABLE_EACEN_RRS Marc Kleine-Budde
2015-09-01 10:31 ` [PATCH 4/8] can: flexcan: reg_imask2_default Marc Kleine-Budde
2015-09-01 10:31 ` [PATCH 5/8] can: rx-fifo: introduce software rx-fifo implementation Marc Kleine-Budde
2015-09-01 10:32 ` [PATCH 6/8] can: flexcan: add support for rx-fifo based software FIFO implementation Marc Kleine-Budde
2015-09-01 10:32 ` [PATCH 7/8] can: flexcan: switch imx6 and vf610 to software based fifo Marc Kleine-Budde
2015-09-01 10:32 ` [PATCH 8/8] can: at91_can: switch to rx-fifo implementation Marc Kleine-Budde
2015-09-02 23:58 ` [PATCH 0/8] RFC: more flexcan cleanups and SW FIFO IRQ offloading Tom Evans
2015-09-03 6:32 ` David Jander
2015-09-03 6:58 ` Marc Kleine-Budde
2015-09-03 8:17 ` Tom Evans [this message]
2015-09-03 8:38 ` David Jander
2015-09-03 8:47 ` Marc Kleine-Budde
2015-09-04 3:19 ` Tom Evans
2015-09-03 8:45 ` Marc Kleine-Budde
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=55E80231.30808@optusnet.com.au \
--to=tom_usenet@optusnet.com.au \
--cc=david@protonic.nl \
--cc=kernel@pengutronix.de \
--cc=linux-can@vger.kernel.org \
--cc=mkl@pengutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.