From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless
Date: Tue, 8 Sep 2015 08:20:59 -0700 [thread overview]
Message-ID: <55EEFCDB.7050705@twiddle.net> (raw)
In-Reply-To: <CAFEAcA9KUzL+LMzYmhpnEhWZvz3paT_tCtMHHFiLd9CFyRoE-g@mail.gmail.com>
On 09/08/2015 01:19 AM, Peter Maydell wrote:
> The tcg common code isn't smart enough to notice it only
> needs to calculate not(t1) once ?
Correct, we do no value numbering or cse.
> In the overwhelmingly common case (x86 tcg backend)
> we would save an insn every time, right?
Yes. It all depends on what value is used for NZCV, of course.
Thankfully we *do* do dead code elimination, which is why I unconditionally
compute both T1 and T2, and let them be deleted should they be unused.
> I wouldn't bother to make the front-end generate different
> code for the backend does/doesn't have andc situations,
> certainly.
I'll mock it up and see how much duplication there is. And also check it out
on a Haswell host, which does have andc.
r~
next prev parent reply other threads:[~2015-09-08 15:21 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-02 17:57 [Qemu-devel] [PATCH v2 00/11] target-arm improvements for aarch64 Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 01/11] target-arm: Share all common TCG temporaries Richard Henderson
2015-09-07 16:57 ` Peter Maydell
2015-09-08 5:13 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 02/11] target-arm: Introduce DisasCompare Richard Henderson
2015-09-07 17:09 ` Peter Maydell
2015-09-08 5:09 ` Richard Henderson
2015-09-08 8:13 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 03/11] target-arm: Handle always condition codes within arm_test_cc Richard Henderson
2015-09-07 17:11 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 04/11] target-arm: Use setcond and movcond for csel Richard Henderson
2015-09-07 17:17 ` Peter Maydell
2015-09-08 5:12 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless Richard Henderson
2015-09-07 17:31 ` Peter Maydell
2015-09-08 5:18 ` Richard Henderson
2015-09-08 8:19 ` Peter Maydell
2015-09-08 15:20 ` Richard Henderson [this message]
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond Richard Henderson
2015-09-07 17:42 ` Peter Maydell
2015-09-08 15:21 ` Richard Henderson
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR Richard Henderson
2015-09-07 17:47 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL Richard Henderson
2015-09-07 18:00 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Richard Henderson
2015-09-07 18:02 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 10/11] target-arm: Recognize ROR Richard Henderson
2015-09-07 18:06 ` Peter Maydell
2015-09-02 17:57 ` [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32 Richard Henderson
2015-09-07 18:11 ` Peter Maydell
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