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From: Richard Henderson <rth@twiddle.net>
To: Alvise Rigo <a.rigo@virtualopensystems.com>,
	qemu-devel@nongnu.org, mttcg@greensocs.com
Cc: claudio.fontana@huawei.com, jani.kokkonen@huawei.com,
	tech@virtualopensystems.com, alex.bennee@linaro.org,
	pbonzini@redhat.com
Subject: Re: [Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for excl accesses
Date: Wed, 30 Sep 2015 14:03:59 +1000	[thread overview]
Message-ID: <560B5F2F.9060402@twiddle.net> (raw)
In-Reply-To: <1443083566-10994-5-git-send-email-a.rigo@virtualopensystems.com>

On 09/24/2015 06:32 PM, Alvise Rigo wrote:
> Introduce a set of new runtime helpers do handle exclusive instructions.
> This helpers are used as hooks to call the respective LL/SC helpers in
> softmmu_llsc_template.h from TCG code.
>
> Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com>
> Suggested-by: Claudio Fontana <claudio.fontana@huawei.com>
> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
> ---
>   target-arm/helper.h    | 10 ++++++
>   target-arm/op_helper.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 104 insertions(+)
>
> diff --git a/target-arm/helper.h b/target-arm/helper.h
> index 827b33d..8e7a7c2 100644
> --- a/target-arm/helper.h
> +++ b/target-arm/helper.h
> @@ -530,6 +530,16 @@ DEF_HELPER_2(dc_zva, void, env, i64)
>   DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64)
>   DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
>
> +DEF_HELPER_3(ldlink_aa32_i8, i32, env, i32, i32)
> +DEF_HELPER_3(ldlink_aa32_i16, i32, env, i32, i32)
> +DEF_HELPER_3(ldlink_aa32_i32, i32, env, i32, i32)
> +DEF_HELPER_3(ldlink_aa32_i64, i64, env, i32, i32)
> +
> +DEF_HELPER_4(stcond_aa32_i8, i32, env, i32, i32, i32)
> +DEF_HELPER_4(stcond_aa32_i16, i32, env, i32, i32, i32)
> +DEF_HELPER_4(stcond_aa32_i32, i32, env, i32, i32, i32)
> +DEF_HELPER_4(stcond_aa32_i64, i32, env, i32, i64, i32)
> +
>   #ifdef TARGET_AARCH64
>   #include "helper-a64.h"
>   #endif
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 663c05d..d832ba8 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -969,3 +969,97 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
>           return ((uint32_t)x >> shift) | (x << (32 - shift));
>       }
>   }
> +
> +/* LoadLink helpers, only unsigned. */
> +static void * const qemu_ldex_helpers[16] = {
> +    [MO_UB]   = helper_ret_ldlinkub_mmu,
> +
> +    [MO_LEUW] = helper_le_ldlinkuw_mmu,
> +    [MO_LEUL] = helper_le_ldlinkul_mmu,
> +    [MO_LEQ]  = helper_le_ldlinkq_mmu,
> +
> +    [MO_BEUW] = helper_be_ldlinkuw_mmu,
> +    [MO_BEUL] = helper_be_ldlinkul_mmu,
> +    [MO_BEQ]  = helper_be_ldlinkq_mmu,
> +};
> +
> +#define LDEX_HELPER(SUFF, OPC)                                          \
> +uint32_t HELPER(ldlink_aa32_i##SUFF)(CPUARMState *env, uint32_t addr,   \
> +                                                       uint32_t index)  \
> +{                                                                       \
> +    CPUArchState *state = env;                                          \
> +    TCGMemOpIdx op;                                                     \
> +                                                                        \
> +    op = make_memop_idx(OPC, index);                                    \
> +                                                                        \
> +    tcg_target_ulong (*func)(CPUArchState *env, target_ulong addr,      \
> +                             TCGMemOpIdx oi, uintptr_t retaddr);        \
> +    func = qemu_ldex_helpers[OPC];                                      \
> +                                                                        \
> +    return (uint32_t)func(state, addr, op, GETRA());                    \
> +}
> +
> +LDEX_HELPER(8, MO_UB)
> +LDEX_HELPER(16, MO_TEUW)
> +LDEX_HELPER(32, MO_TEUL)

This is not what Aurelien meant.  I cannot see any reason at present why 
generic wrappers, available for all targets, shouldn't be sufficient.

See tcg/tcg-runtime.h and tcg-runtime.c.

You shouldn't need to look up a function in a table like this.  The decision 
about whether to call a BE or LE helper should have been made in the translator.


r~

  reply	other threads:[~2015-09-30  4:31 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-24  8:32 [Qemu-devel] [RFC v5 0/6] Slow-path for atomic instruction translation Alvise Rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 1/6] exec.c: Add new exclusive bitmap to ram_list Alvise Rigo
2015-09-26 17:15   ` Richard Henderson
2015-09-28  7:28     ` alvise rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 2/6] softmmu: Add new TLB_EXCL flag Alvise Rigo
2015-09-30  3:34   ` Richard Henderson
2015-09-30  9:24     ` alvise rigo
2015-09-30 11:09       ` Peter Maydell
2015-09-30 12:44         ` alvise rigo
2015-09-30 20:37           ` Richard Henderson
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 3/6] softmmu: Add helpers for a new slowpath Alvise Rigo
2015-09-30  3:58   ` Richard Henderson
2015-09-30  9:46     ` alvise rigo
2015-09-30 20:42       ` Richard Henderson
2015-10-01  8:05         ` alvise rigo
2015-10-01 19:34           ` Richard Henderson
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for excl accesses Alvise Rigo
2015-09-30  4:03   ` Richard Henderson [this message]
2015-09-30 10:16     ` alvise rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 5/6] configure: Use slow-path for atomic only when the softmmu is enabled Alvise Rigo
2015-09-30  4:05   ` Richard Henderson
2015-09-30  9:51     ` alvise rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 6/6] target-arm: translate: Use ld/st excl for atomic insns Alvise Rigo
2015-09-30  4:44 ` [Qemu-devel] [RFC v5 0/6] Slow-path for atomic instruction translation Paolo Bonzini
2015-09-30  8:14   ` alvise rigo
2015-09-30 13:20     ` Paolo Bonzini
2015-10-01 19:32   ` Emilio G. Cota

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