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From: Richard Henderson <rth@twiddle.net>
To: alvise rigo <a.rigo@virtualopensystems.com>
Cc: mttcg@greensocs.com,
	"Claudio Fontana" <claudio.fontana@huawei.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Jani Kokkonen" <jani.kokkonen@huawei.com>,
	"VirtualOpenSystems Technical Team" <tech@virtualopensystems.com>,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [RFC v5 3/6] softmmu: Add helpers for a new slowpath
Date: Fri, 2 Oct 2015 05:34:35 +1000	[thread overview]
Message-ID: <560D8ACB.3070809@twiddle.net> (raw)
In-Reply-To: <CAH47eN3n1fBCL5rS39jJqJiFk6PLeu60AGYTYszoGLpdsiEtVA@mail.gmail.com>

On 10/01/2015 06:05 PM, alvise rigo wrote:
> On Wed, Sep 30, 2015 at 10:42 PM, Richard Henderson <rth@twiddle.net> wrote:
>>
>> On 09/30/2015 07:46 PM, alvise rigo wrote:
>>>
>>> On Wed, Sep 30, 2015 at 5:58 AM, Richard Henderson <rth@twiddle.net> wrote:
>>>>
>>>> Why would you need to indicate that another cpu has started an exclusive
>>>> operation on this page?  That seems definitely wrong.
>>>
>>>
>>> The cpu_physical_memory_clear_excl_dirty() sets the flag to generate
>>> the TLB entry with the EXCL flag.
>>
>>
>> Yes, but surely the clearing of dirty on current_cpu is enough to cause the other cpus to see that they need to set TLB_EXCL when reloading their tlb entries.
>>
>> Why do you need to manipulate the *other* cpu's dirty bit?
>
> Because then we can assume that a cpu with the bit cleared has for
> sure the TLB entries with the EXCL flag set for that specific page.
> Moreover, knowing which cpus have the EXCL flag set allows to reduce
> the flushing requests whenever a new LL is issued on the same page.

Does it actually help, or is that a guess without numbers?


r~

  reply	other threads:[~2015-10-01 19:34 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-24  8:32 [Qemu-devel] [RFC v5 0/6] Slow-path for atomic instruction translation Alvise Rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 1/6] exec.c: Add new exclusive bitmap to ram_list Alvise Rigo
2015-09-26 17:15   ` Richard Henderson
2015-09-28  7:28     ` alvise rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 2/6] softmmu: Add new TLB_EXCL flag Alvise Rigo
2015-09-30  3:34   ` Richard Henderson
2015-09-30  9:24     ` alvise rigo
2015-09-30 11:09       ` Peter Maydell
2015-09-30 12:44         ` alvise rigo
2015-09-30 20:37           ` Richard Henderson
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 3/6] softmmu: Add helpers for a new slowpath Alvise Rigo
2015-09-30  3:58   ` Richard Henderson
2015-09-30  9:46     ` alvise rigo
2015-09-30 20:42       ` Richard Henderson
2015-10-01  8:05         ` alvise rigo
2015-10-01 19:34           ` Richard Henderson [this message]
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for excl accesses Alvise Rigo
2015-09-30  4:03   ` Richard Henderson
2015-09-30 10:16     ` alvise rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 5/6] configure: Use slow-path for atomic only when the softmmu is enabled Alvise Rigo
2015-09-30  4:05   ` Richard Henderson
2015-09-30  9:51     ` alvise rigo
2015-09-24  8:32 ` [Qemu-devel] [RFC v5 6/6] target-arm: translate: Use ld/st excl for atomic insns Alvise Rigo
2015-09-30  4:44 ` [Qemu-devel] [RFC v5 0/6] Slow-path for atomic instruction translation Paolo Bonzini
2015-09-30  8:14   ` alvise rigo
2015-09-30 13:20     ` Paolo Bonzini
2015-10-01 19:32   ` Emilio G. Cota

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