Re: [PATCH v3] x86/EPT: work around hardware erratum setting A bit

[Andrew Cooper <andrew.cooper3@citrix.com>]

On 30/09/15 13:02, Jan Beulich wrote:
>>>> On 30.09.15 at 13:47, <andrew.cooper3@citrix.com> wrote:
>> On 30/09/15 12:36, Jan Beulich wrote:
>>> Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for
>>> log-dirty"), the A and D bits of EPT paging entries are set
>>> unconditionally, regardless of whether PML is enabled or not. This
>>> causes a regression in Xen 4.6 on some processors due to Intel Errata
>>> AVR41 -- HVM guests get severe memory corruption when the A bit is set
>>> due to incorrect TLB flushing on mov to cr3. The errata affects the Atom
>>> C2000 family (Avoton).
>>>
>>> To fix, do not set the A bit on this processor family.
>>>
>>> Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com>
>>>
>>> Move feature suppression to feature detection code. Add command line
>>> override.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>>
>>> --- a/docs/misc/xen-command-line.markdown
>>> +++ b/docs/misc/xen-command-line.markdown
>>> @@ -705,19 +705,28 @@ virtualization, to allow the L1 hypervis
>>>  does not provide VM\_ENTRY\_LOAD\_GUEST\_PAT.
>>>  
>>>  ### ept (Intel)
>>> -> `= List of ( pml<boolean> )`
>>> +> `= List of ( pml | ad )`
>> Please keep the type annotations.  Future sub-options might not be
>> boolean parameters.
> None of the three other examples (efi, iommu, and pci) have such
> annotations. If anything, I'd lean towards the way pci is being
> described.

Oh - they are missing.  Going with the PCI route seems like a good way
forwards.

>
>> Otherwise, Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
> Let me know.

Given I was mistaken about the other tags, consider this an
unconditional review, although a modification towards the PCI route
would be nice.

~Andrew