Re: [PATCH v3] x86/EPT: work around hardware erratum setting A bit

[Kai Huang <kai.huang@linux.intel.com>]

On 10/02/2015 05:36 PM, Wei Liu wrote:
> On Wed, Sep 30, 2015 at 01:25:49PM +0100, Wei Liu wrote:
>> On Wed, Sep 30, 2015 at 05:36:22AM -0600, Jan Beulich wrote:
>>> Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for
>>> log-dirty"), the A and D bits of EPT paging entries are set
>>> unconditionally, regardless of whether PML is enabled or not. This
>>> causes a regression in Xen 4.6 on some processors due to Intel Errata
>>> AVR41 -- HVM guests get severe memory corruption when the A bit is set
>>> due to incorrect TLB flushing on mov to cr3. The errata affects the Atom
>>> C2000 family (Avoton).
>>>
>>> To fix, do not set the A bit on this processor family.
>>>
>>> Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com>
>>>
>>> Move feature suppression to feature detection code. Add command line
>>> override.
>>>
>>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>>>
>> Release-acked-by: Wei Liu <wei.liu2@citrix.com>
>>
>> Thanks for handling this issue!
> In light of both the author and vmx maintainer are on vacation until
> October 8, I think we might as well commit this today.
>
> Kevin and Kai, when you're back, please have a look at this patch. And,
> if you disagree with the approach, please provide a patch to be
> backported to 4.6.1.
Hi Wei,

Sorry for late response. Our QA (Xudong and Robert, also copied here) 
has conducted PML testing on Xen 4.6 release (which contains this patch) 
and looks everything works fine.

Thanks,
-Kai
>
> Wei.
>