Re: [Qemu-devel] [PATCH] target-mips: Add more reg numbers for RDHWR

[Leon Alrae <leon.alrae@imgtec.com>]

On 05/10/15 13:48, Yongbok Kim wrote:
> Add more register numbers for RDHWR

Could the commit message say which registers exactly this patch is adding?

> Add check_hwrena() to simplify access control checkings.
> Add RDHWR support to microMIPS R6
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---

> @@ -1357,6 +1357,12 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
>  {
>      uint32_t mask = 0x0000000F;
>  
> +    if (env->CP0_Config1 & (1 << CP0C1_PC)) {
> +        mask |= (1 << 4);
> +    }

I think we should check also for ISA_MIPS32R6 here. The access to
CP0.PerfCnt via RDHWR was added in R6 and before that the register
number 4 in HWREna was reserved.

Otherwise looks good to me.

Thanks,
Leon