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From: guohanjun@huawei.com (Hanjun Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] EDAC: Add AMD Seattle SoC EDAC
Date: Wed, 21 Oct 2015 09:55:43 +0800	[thread overview]
Message-ID: <5626F09F.4050107@huawei.com> (raw)
In-Reply-To: <20151020173639.GH31130@pd.tnic>

Hi Boris, Mark,

On 2015/10/21 1:36, Borislav Petkov wrote:
> On Tue, Oct 20, 2015 at 06:26:55PM +0100, Mark Rutland wrote:
>>> Btw, how much of this is implementing generic A57 functionality?
>> The driver is entirely A57 generic.
>>
>>> If a lot, can we make this a generic a57_edac driver so that multiple
>>> vendors can use it?
>> Yes.
> Ok, cool.
>
>>> How fast and how ugly can something like that become?
>> Not sure I follow.
> In the sense that some vendor might require just a little bit different
> handling or maybe wants to read some vendor-specific registers in
> addition to the architectural ones.

Yes, you are right and foresight :)

>
> Then we'll start adding vendor-specific hacks to that generic driver.
> And therefore the question how fast and how ugly such hacks would
> become.
>
> I guess we'll worry about that when we get there...

So I think the meaning of those error register is the same, but the way
of handle it may different from SoCs, for single bit error:

 - SoC may trigger a interrupt;
 - SoC may just keep silent so we need to scan the registers using poll
   mechanism.

For Double bit error:
  - SoC may also keep silent
  - Trigger a interrupt
  - Trigger a SEI (system error)

Any suggestion to cover those cases?

Thanks
Hanjun

WARNING: multiple messages have this Message-ID (diff)
From: Hanjun Guo <guohanjun@huawei.com>
To: Borislav Petkov <bp@alien8.de>, Mark Rutland <mark.rutland@arm.com>
Cc: Brijesh Singh <brijeshkumar.singh@amd.com>,
	Arnd Bergmann <arnd@arndb.de>,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
	robh+dt@kernel.org, pawel.moll@arm.com,
	ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
	dougthompson@xmission.com, mchehab@osg.samsung.com,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	Huxinwei <huxinwei@huawei.com>
Subject: Re: [PATCH] EDAC: Add AMD Seattle SoC EDAC
Date: Wed, 21 Oct 2015 09:55:43 +0800	[thread overview]
Message-ID: <5626F09F.4050107@huawei.com> (raw)
In-Reply-To: <20151020173639.GH31130@pd.tnic>

Hi Boris, Mark,

On 2015/10/21 1:36, Borislav Petkov wrote:
> On Tue, Oct 20, 2015 at 06:26:55PM +0100, Mark Rutland wrote:
>>> Btw, how much of this is implementing generic A57 functionality?
>> The driver is entirely A57 generic.
>>
>>> If a lot, can we make this a generic a57_edac driver so that multiple
>>> vendors can use it?
>> Yes.
> Ok, cool.
>
>>> How fast and how ugly can something like that become?
>> Not sure I follow.
> In the sense that some vendor might require just a little bit different
> handling or maybe wants to read some vendor-specific registers in
> addition to the architectural ones.

Yes, you are right and foresight :)

>
> Then we'll start adding vendor-specific hacks to that generic driver.
> And therefore the question how fast and how ugly such hacks would
> become.
>
> I guess we'll worry about that when we get there...

So I think the meaning of those error register is the same, but the way
of handle it may different from SoCs, for single bit error:

 - SoC may trigger a interrupt;
 - SoC may just keep silent so we need to scan the registers using poll
   mechanism.

For Double bit error:
  - SoC may also keep silent
  - Trigger a interrupt
  - Trigger a SEI (system error)

Any suggestion to cover those cases?

Thanks
Hanjun

WARNING: multiple messages have this Message-ID (diff)
From: Hanjun Guo <guohanjun@huawei.com>
To: Borislav Petkov <bp@alien8.de>, Mark Rutland <mark.rutland@arm.com>
Cc: Brijesh Singh <brijeshkumar.singh@amd.com>,
	Arnd Bergmann <arnd@arndb.de>, <linux-kernel@vger.kernel.org>,
	<linux-edac@vger.kernel.org>, <robh+dt@kernel.org>,
	<pawel.moll@arm.com>, <ijc+devicetree@hellion.org.uk>,
	<galak@codeaurora.org>, <dougthompson@xmission.com>,
	<mchehab@osg.samsung.com>, <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, Huxinwei <huxinwei@huawei.com>
Subject: Re: [PATCH] EDAC: Add AMD Seattle SoC EDAC
Date: Wed, 21 Oct 2015 09:55:43 +0800	[thread overview]
Message-ID: <5626F09F.4050107@huawei.com> (raw)
In-Reply-To: <20151020173639.GH31130@pd.tnic>

Hi Boris, Mark,

On 2015/10/21 1:36, Borislav Petkov wrote:
> On Tue, Oct 20, 2015 at 06:26:55PM +0100, Mark Rutland wrote:
>>> Btw, how much of this is implementing generic A57 functionality?
>> The driver is entirely A57 generic.
>>
>>> If a lot, can we make this a generic a57_edac driver so that multiple
>>> vendors can use it?
>> Yes.
> Ok, cool.
>
>>> How fast and how ugly can something like that become?
>> Not sure I follow.
> In the sense that some vendor might require just a little bit different
> handling or maybe wants to read some vendor-specific registers in
> addition to the architectural ones.

Yes, you are right and foresight :)

>
> Then we'll start adding vendor-specific hacks to that generic driver.
> And therefore the question how fast and how ugly such hacks would
> become.
>
> I guess we'll worry about that when we get there...

So I think the meaning of those error register is the same, but the way
of handle it may different from SoCs, for single bit error:

 - SoC may trigger a interrupt;
 - SoC may just keep silent so we need to scan the registers using poll
   mechanism.

For Double bit error:
  - SoC may also keep silent
  - Trigger a interrupt
  - Trigger a SEI (system error)

Any suggestion to cover those cases?

Thanks
Hanjun


  parent reply	other threads:[~2015-10-21  1:55 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-19 19:23 [PATCH] EDAC: Add AMD Seattle SoC EDAC Brijesh Singh
2015-10-19 19:23 ` Brijesh Singh
2015-10-19 20:14 ` Borislav Petkov
2015-10-19 20:14   ` Borislav Petkov
2015-10-19 20:52 ` Mark Rutland
2015-10-19 20:52   ` Mark Rutland
2015-10-20 16:44   ` Brijesh Singh
2015-10-20 16:44     ` Brijesh Singh
2015-10-20 16:44     ` Brijesh Singh
2015-10-20 16:57     ` Borislav Petkov
2015-10-20 16:57       ` Borislav Petkov
2015-10-20 16:57       ` Borislav Petkov
2015-10-20 17:26       ` Mark Rutland
2015-10-20 17:26         ` Mark Rutland
2015-10-20 17:26         ` Mark Rutland
2015-10-20 17:36         ` Borislav Petkov
2015-10-20 17:36           ` Borislav Petkov
2015-10-20 17:41           ` Mark Rutland
2015-10-20 17:41             ` Mark Rutland
2015-10-20 17:41             ` Mark Rutland
2015-10-20 19:16             ` Brijesh Singh
2015-10-20 19:16               ` Brijesh Singh
2015-10-20 19:16               ` Brijesh Singh
2015-10-21  1:55           ` Hanjun Guo [this message]
2015-10-21  1:55             ` Hanjun Guo
2015-10-21  1:55             ` Hanjun Guo
2015-10-21  9:35             ` Borislav Petkov
2015-10-21  9:35               ` Borislav Petkov
2015-10-21  9:35               ` Borislav Petkov
2015-10-21 10:01               ` Andre Przywara
2015-10-21 10:01                 ` Andre Przywara
2015-10-21 10:01                 ` Andre Przywara
2015-10-21 16:22                 ` Brijesh Singh
2015-10-21 16:22                   ` Brijesh Singh
2015-10-21 16:22                   ` Brijesh Singh
2015-10-23  1:38               ` Hanjun Guo
2015-10-23  1:38                 ` Hanjun Guo
2015-10-23  1:38                 ` Hanjun Guo
2015-10-20 17:25     ` Mark Rutland
2015-10-20 17:25       ` Mark Rutland
2015-10-20 17:25       ` Mark Rutland
2015-10-21  1:45       ` Hanjun Guo
2015-10-21  1:45         ` Hanjun Guo
2015-10-21  1:45         ` Hanjun Guo
2015-10-20  2:21 ` Hanjun Guo
2015-10-20  2:21   ` Hanjun Guo
2015-10-20 21:26   ` Brijesh Singh
2015-10-20 21:26     ` Brijesh Singh
2015-10-21  1:35     ` Hanjun Guo
2015-10-21  1:35       ` Hanjun Guo

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