From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options
Date: Fri, 23 Oct 2015 12:56:51 -0600 [thread overview]
Message-ID: <562A82F3.3060309@wwwdotorg.org> (raw)
In-Reply-To: <1444987441-25176-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 10/16/2015 03:24 AM, Jon Hunter wrote:
> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124
> documentation implies that all functions (pcie, usb3 and sata) can be
> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has
> been confirmed that this is not the case and the mux'ing options much more
> limited. Unfortunately, the public documentation has not been updated to
> reflect this and so detail the actual mux'ing options here by function:
>
> Function: Lanes:
> pcie1 x2: pcie3, pcie4
> pcie1 x4: pcie1, pcie2, pcie3, pcie4
> pcie2 x1 (option1): pcie0
> pcie2 x1 (option2): pcie2
> usb3 port 0: pcie0
> usb3 port 1 (option 1): pcie1
> usb3 port 1 (option 2): sata0
> sata: sata0
Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
I didn't check the actual lists of values, but it sounds about right
from memory.
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren@wwwdotorg.org>
To: Jon Hunter <jonathanh@nvidia.com>,
Linus Walleij <linus.walleij@linaro.org>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>,
linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options
Date: Fri, 23 Oct 2015 12:56:51 -0600 [thread overview]
Message-ID: <562A82F3.3060309@wwwdotorg.org> (raw)
In-Reply-To: <1444987441-25176-1-git-send-email-jonathanh@nvidia.com>
On 10/16/2015 03:24 AM, Jon Hunter wrote:
> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124
> documentation implies that all functions (pcie, usb3 and sata) can be
> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has
> been confirmed that this is not the case and the mux'ing options much more
> limited. Unfortunately, the public documentation has not been updated to
> reflect this and so detail the actual mux'ing options here by function:
>
> Function: Lanes:
> pcie1 x2: pcie3, pcie4
> pcie1 x4: pcie1, pcie2, pcie3, pcie4
> pcie2 x1 (option1): pcie0
> pcie2 x1 (option2): pcie2
> usb3 port 0: pcie0
> usb3 port 1 (option 1): pcie1
> usb3 port 1 (option 2): sata0
> sata: sata0
Acked-by: Stephen Warren <swarren@nvidia.com>
I didn't check the actual lists of values, but it sounds about right
from memory.
next prev parent reply other threads:[~2015-10-23 18:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-16 9:24 [PATCH] pinctrl: tegra-xusb: Correct lane mux options Jon Hunter
[not found] ` <1444987441-25176-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-10-16 16:17 ` Stephen Warren
2015-10-16 16:17 ` Stephen Warren
2015-10-19 11:41 ` Jon Hunter
2015-10-19 11:41 ` Jon Hunter
2015-10-20 11:28 ` Jon Hunter
2015-10-20 11:28 ` Jon Hunter
2015-10-20 16:08 ` Stephen Warren
2015-10-20 18:02 ` Jon Hunter
2015-10-20 18:02 ` Jon Hunter
2015-10-20 18:36 ` Stephen Warren
2015-10-23 7:22 ` Jon Hunter
2015-10-23 7:22 ` Jon Hunter
2015-10-23 18:56 ` Stephen Warren [this message]
2015-10-23 18:56 ` Stephen Warren
2015-10-27 16:07 ` Linus Walleij
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